Low-Power Physical Design For A14-bit DEM D/A Converter

High-speed high-resolution digital-to-analog converter (DAC) is widely used for wireless communication and video signal processing, most high-speed DACs are based on current-steering architectures which use unit element current sources for the conversion. The static performance of DAC is limited by the process mismatches, which can be minimized by dynamic element matching (DEM) technique. DEM is widely used in multibit DACs to prevent mismatches among nominally identical components from introducing nonlinear distortion. A segmented DEM technique allows an efficient tradeoff between encoder complexity and the number of unit current-steering cells.Based on the SMIC0.18μm1P6M standard CMOS process, a14-bit high-speed segmented current-steering D/A converter is designed in this thesis. The sampling clock frequency is1GHz, and the segmented structure is5-5-4. The5most significant bits and the5intermediate significant bits use a low logic complexity, high-speed and random adjustable DEM decoding technique. The D/A converter is designed by using standard mixed analog-digital ASIC flow, and the layout of analog module is individually designed and made macro cell. The design of the DEM decoding circuit includes algorithm design, logic synthesis, physical implementation and timing verification. High-speed pipeline design of the encoder make high slew rate of the D/A converter possible. Using the low-power design methodology of clock gating insertion and operand isolation logic-level when doing Logic synthesis. D/A converter of physical implementation process includes Floorplan, Clock Tree Synthesis and Routing, while considering the requirements of low-power design, crosstalk repairing and antenna effects prevention.The design of DEM D/A converter requires800MHz sampling clock frequency, less2mm2area, less0.5W power. Final sign-off verification results meet design timing, area and power requirements, wherein the DEM decoder circuit using4446standard cells, the layout area of decoder about0.15mm2, the layout area of the D/A converter about1.1mm×1.3mm. The sampling clock frequency can reach1GHz on the worst condition, and total power about400mW.