Soc Physical Design Low Power Consumption In Power Supply Network Analysis And Research

With the level of technology more and more advanced, the development of integrated circuits goes into the SOC(System On Chip) area. scale increasing, the chip reaches billions of gates. It’s need to be addressed such a large-scale transistors bring power consumption issues. Physical design takes an important role in the integrated circuit design. Power network, which is an important procedure in physical design, whose performance will directly affect digital integrated circuit chip system work or not.The study of power network has important significance. In this paper, we study the power consumption of the SOC physical design.This paper firstly analyzes the theory of the composition of the power during the integrated circuit design, describes factors about static power and dynamic power consumption. Secondly, it takes consideration from the device structure to deduce the static power consumption as well as it takes calculation of the dynamic power consumption in the switching power and short-circuit power. Then, the article summarizes the direction optimization about the low-power design. Based on the study of the SOC power consumption principle, using TCL command compile CPF (common power format),which contains, such as, the multi-power domain, the power supply shut off, the dynamic voltage frequency scaling, low-power design methods. Next, according to the result of Floorplan.it used EPS design power grid view, the different power supply network lines static voltage IR drop at the physical design stage. Ultimately, the article ensures the design of the chip to meet the requirements of power network distribution. Make sure dynamic voltage IR drop and the static IR drop less than3%of the source.