| With the rapid development of digital integrated circuits,the performance requirements of the analog to digital converter(ADC)are also increasing,which is as a bridge connecting analog and digital.ADCs used in medical and imaging equipment usually require high accuracy,which results in high power consumption.At present,the market tends to be lower in power consumption,so the research on low power consumption of high-precision ADCs is becoming more and more important.The purpose of this paper is to design a low-cost,high-performance analog-to-digital converter for market applications.The mature 0.5μm process is used to control the cost.The structure of the operational amplifier(op amp)sharing and the step-by-step reduction of the capacitor is adopted to reduce power consumption,and the precision of 14 bits is achieved by digital calibration module.The main work includes:(1)The core op amp of pipeline ADC adopts the telescopic cascode structure to reduce the current branches and achieve the purpose of reducing power consumption.At the same time,in order to meet the requirements of gain and avoid the reduction of accuracy caused by finite gain,the auxiliary op amp is added.Reasonably design the bandwidth of the auxiliary op amp to ensure the high gain without affecting the stability of the system.The structure of the op amp sharing between two adjacent stages,and the capacitance is gradually decreased step by step are atlopted,to reduce the power consumption of the system.The memory effect of charge will be brought by the structure of op amp sharing.Zero clock signal is added through the design of non-overlapping dock to eliminate the influence.(2)In this paper,the sampling and holding circuit selects charge transfer structure to double the amplification of the input signal,which is used to reduce the demand for the post·stage comparator offset.In addition,the same common mode voltage of input and output of op amp is avoided by using this structure,which makes the design of op amp more flexible.Based on the TSMC 0.5μm CMOS process,through the improvement of the core op amp,and the use of op amp sharing,the design of low-cost,low-power 14-bit 65MHz pipeline ADC is completed.In the layout process of the layout,considering the mismatchs,a reasonable choice is made for the layout of the capacitor and the op amp input MOS tube.The post-simulation results show that under the Nyquist sampling,the effective bit of the system is 13.45 bit,SFDR is 100dB,SNR is 82.749dB,and the power consumption is 66.5mA under the 27℃,tt process angle,which achieved the goal of reducing power consumption while satisfying accuracy,and achieved the desired goals. |
