Research On Time-domain Comparator-based High-Resolution Low-power SAR ADC

Along with the booming development of Internet of Things,wearable devices and medical electronics,a large number of sensors are deployed and used,and analog-todigital converters play a key role in sensor networks as a bridge between analog and digital signals.These application scenes often require high-resolution,low-power analogto-digital converters to work continuously,and most of the SAR ADCs that are adapted to advanced CMOS processes are composed of digital blocks and provide high energy efficiency.So it is receiving more and more attention.At the same time,in the SAR ADC,the time domain comparator which is relatively insensitive to supply voltage and superior in noise performance has become a hot spot for high-precision design,and the VCObased comparator can not only obtain the comparison result.Additional oscillating information can be utilized for other functions,such as in implementing bypass window logic.In this paper,the performance specifications,main blocks and related technologies of this design are introduced in detail.Based on this,a 12-bit SAR ADC under 1.1V supply voltage is designed in 40 nm CMOS process.The ADC uses a VCO-based comparator to implement bypass logic and metastable detection logic,and the skipped comparison cycles save a lot of energy.In addition,this paper proposes a Split-andRecombination redundancy and corresponding digital correction logic used in the bypass logic to improve the overall accuracy and speed of the ADC.The circuit simulation results show that the ENOB of the design is 11.12 bit,the SFDR is 85.35 dB,and the FoM is 5.69fJ/Conv.at a supply voltage of 1.1V and sampling rate of 30MS/s.It achieves high energy efficiency.Compared to SAR ADCs using a single time domain comparator,this design is the highest speed among the literatures.