Research And Implementation Of LDPC Decoding Algorithm Based On ZYNQ

With the development of global navigation satellite system(GNSS),the communication system not only requires high reliability,but also has more and more stringent requirements in terms of effectiveness.As the representative of the third generation forward error correction(FEC)technology,Low-Density Parity-Check(LDPC)code is widely used in satellite communication field.Its error performance approaches Shannon limit,its encoding and decoding algorithm is flexible and can complete parallel operation.Its hardware implementation is simple and easy.It has become a hot spot of research and application at present.For most navigation signals,the long transmission distance leads to the large power consumption when the signal lands,and is seriously disturbed by complex natural noise,which makes the navigation message can not be demodulated normally.Therefore,in order to adapt to the harsh and changeable environment,error correction coding is usually used to design navigation message,which effectively improves the coding gain and improves the demodulation performance.The navigation message of Beidou navigation satellite system(BDS)uses multi-level LDPC coding,which provides a higher performance LDPC decoder accurately and efficiently to meet the needs of users.Firstly,three classical decoding algorithms are analyzed and compared.Aiming at the shortcomings of the classical algorithms,such as large amount of computation and difficult hardware implementation,an improved extended minimum sum decoding algorithm based on the minimum sum decoding algorithm is proposed.Based on the related research of the extended minimum sum decoding algorithm as the theoretical support,its decoding performance and related decoding parameters are simulated and confirmed by python.In terms of hardware implementation,the scalable heterogeneous processing chip Zynq7100 is used as the hardware implementation platform,and the ideas and solutions of the software and hardware co-design of the decoder is explored.Afterwards,the software control process and each core module of the decoder is combed in detail,and the structure principle of each module is emphatically explained.Finally,in the development environment of Vivado 2019.1,the design logic of each functional module is clarified,and the circuit description is carried out using the Verilog HDL hardware description language.Meanwhile,the software is designed by C language,and the functional verification of each module is combined with the simulation file,so that the results of decoding meet the requirements.