Research On High Speed Encoder And Decoder Of Nonbinary LDPC Codes

LDPC code,as a channel coding method with the performance closest to Shannon limit,plays an important role in error correction coding.Research shows that nonbinary LDPC codes based on high-order finite field GF(q)(q>2)have better error correction performance than binary LDPC codes in the field of medium and short codes,and it is easy to combine high-order modulation into an efficient code modulation system.However,along with this performance advantage is the improvement of coding complexity and the requirement of hardware resources.In this paper,the construction of nonbinary LDPC code and the low complexity encoding and decoding algorithm are studied and simulated,and the decoder is implemented on FPGA.First,based on the basic theory of finite fields,this article gives an overview of nonbinary LDPC codes,focusing on quasi-cyclic nonbinary LDPC codes.Then the construction method of nonbinary LDPC code and the coding and decoding algorithm are studied,and the complexity,advantages and disadvantages of different algorithms are compared.A regular quasi-cyclic nonbinary LDPC code with a code length of 120 symbols and a code rate of 0.5 is constructed in GF(16)domain by using the construction method of multiplication group in finite field and random masking.Secondly,the coding and modulation system of nonbinary LDPC code is introduced.After describing the basic model of the system,the The LDPC code in GF(16)domain is combined with 16-QAM modulation mode.The bit error rate of different decoding algorithms is analyzed by MATLAB simulation,and the extended min-sum decoding algorithm based on bubble check is selected for the hardware implementation of decoder,and the key parameters,including the length of message vector,the number of iterations and quantization bits,are determined.Finally,the nonbinary LDPC code decoder is implemented on the FPGA.The decoder adopts a partial parallel architecture.According to the structure of check matrix,the parallelism of row and column is set to 4 and 8 respectively.After the overall framework is determined,the design and behavior simulation of each sub-module are carried out to verify the normal operation.Then the whole decoder is debugged on the board,and the clock frequency is set to 200 MHz.The test results prove that the decoder can decode correctly and the throughput reaches 7.5Mbps.Finally,a comprehensive report of the decoder is given,and the key factors to improve the throughput are analyzed.