Design And Implemention Of Adaptive Low-density Parity-check(LDPC) Code Decoder

How to maximize the effectiveness of systems while ensuring reliability is one of the topics in the field of communication. To ensure reliability, systems usually use channel coding techniques. Low-density parity check code(LDPC code) has strong error correction capability and lower error floor, and this channel coding scheme draws great attention. To improve the effectiveness, adaptive technology could dynamically adjust transmission parameters, according to the conditions of the channel state, which can effectively improve the system bandwidth utilization. The adaptive communication system based on LDPC codes could both guarantee transmission quality and utilize bandwidth resources effectively. These suggest a great value research.This thesis first introduces the basic theory of LDPC codes and the construction of check matrix, and then it analyzes the properties of the quasi-cyclic(QC-LDPC) codes matrix and the coding algorithm. Research is done about the principle of LDPC code hard decision decoding and soft decision decoding algorithm. The computational complexity and hardware implementation of various decoding algorithms are also analyzed and compared in this thesis. It also compares the error correcting performance and complexity of various decoding algorithm’s simulation result, and chooses GDBF decoding algorithm and normalized min-sum decoding algorithm as the hardware realization scheme. The decoding process of GDBF algorithm is improved, and the steps of calculating objective function is simplified when the multi-bit decoding mode switches to the single-bit decoding mode, and this makes the algorithm more suitable for hardware implementation.Secondly, this thesis simulates the decoder adaptive parameters: the modulation order, code length, code rate and the maximum number of iterations. Analysis is done about the influence on the decoding performance. Based on SNR’s threshold discriminant method, and referring to the simulation results of SNR-BER, the scheme of adaptive decoder is determined corresponding to different channel states. Simulation and analysis are realized for coefficients needed by hardware implementation such as the normalized coefficients and the initial information quantization scheme etc. These work determines the decoder hardware implementation scheme.Finally, combining the structural characteristics of QC-LDPC code’s check matrix and taking into consideration of the design requirements of adaptive decoder, adaptive LDPC decoder based on the normalized min-sum decoding algorithm decoder and improved GDBF decoding algorithm decoder is realized by using the partial parallel architecture. The decoder could flexibly configure code length and code rate and adjust the maximum number of iterative decoding according to the adaptive scheme by changing check matrix H. Based on the overall design of the decoder, the function of each module is divided. LDPC decoder which supports 12 kinds of configuration mode is obtained, and it has passed the function simulation. LDPC decoder eventually completes the board level test decoder by using hardware platform Terasic DE3. The average throughput of normalized min-sum decoding algorithm could reach more than 400 Mbps, and improved GDBF decoding algorithm could reach more than 1Gbps. Therefore the hardware resource consumption is relatively low.