Research And Implementation Of LDPC Decoder For GMR-13G System

With the development of communication technology,satellite communication has become an important communication method.The European Telecommunications Standards Institute(ETSI)released the satellite mobile communication air interface technical specification,that is,the GMR-1 3G standard(GMR,Geostationary earth orbit Mobile Radio interface),which is supported by satellite communication systems of many new generation.In this communication system,how to ensure good channel decoding is an important problem to be solved.Since the discovery of Low Density Parity Check Codes(LDPC codes),it has been widely used in many fields due to its good performance close to the Shannon limit,and it has been a research hot spot in the field of channel coding.Although researchers have made great progress in LDPC decoding theory research at present,in practical applications,there are still many problems that need to be solved such as finding better decoding algorithms,reducing the complexity of the decoder,and supporting more code rates.In view of this phenomenon,this paper studies the existing LDPC decoding algorithm and decoder implementation method.Based on this,the paper proposes an improved decoding algorithm,and designs a multi-code LDPC decoder supporting GMR-1 3G standard using FPGA.The specific work of this paper is as follows:Firstly,this paper studies the Belief Propagation(BP)algorithm,the Log-Likelihood Ratios BP(LLR-BP)algorithm,the Min-Sum(MS)algorithm,and the improved form of Min-Sum algorithm,that is,the Single Normalization Coefficient Min-Sum(SNCMS)algorithm,and gives the simulation results of the performance of several decoding algorithms.Then,this paper studies the source of performance loss in the SNCMS algorithm.Aiming at this performance loss and considering the actual requirements of implementation,this paper proposes the Multiple Normalization Coefficient Min-Sum(MNCMS)algorithm.This proposed algorithm flexibly adopts multi-level normalization coefficients for correction during the check node operation,and obtains better decoding performance than the SNCMS algorithm with a small increase in calculation complexity.Finally,this paper studies three existing architectures of LDPC decoders,which are full parallel architecture,part-parallel architecture,and serial architecture,and selects the appropriate serial architecture for the Irregular Repeat Accumulate LDPC(IRA-LDPC)codes used in the GMR-1 3G standard,designs a universal memory structure that can adapt to a variety of LDPC codes,and gives a decoder implementation that supports all 18 kinds of code with low complexity and high degree of resource reuse.Based on the above-mentioned implementation schemes,this paper designs and implements a multi-code serial IRA-LDPC decoder suitable for GMR-1 3G standard on FPGA.Experimental results show that the decoder can correctly implement the LDPC decoding function.