Research And Implementation Of High Speed LDPC Decoder For Near-Space Communication System

Channel coding is widely used in modern communication systems.Owing to its excellent error-correction and capacity-approaching capability,low-density parity-check codes have been widely adopted in recent standards,such as 10GBSAE-T standard for 10-Gbit Ethernet(IEEE 802.3an),satellite broadcasting(DVB-S2).Among numerous decoding algorithms,min-sum algorithm is widely used since it is hardware friendly.In the design of LDPC decoders based on min-sum algorithms,one of the major problems is to determine the first two minima and the index of the minimum value among many inputs.In this article,the author proposes a general structure to generate the minimum value an approximate second minimum value.Theoretical analysis and simulation results demonstrate that the proposed structure can not only obtain the exact second minimum value with high probability,but also significantly reduce the hardware complexity.Furthermore,mixed radix architecture is investigated carefully in this article.Implemented in a SMIC 65 nm CMOS technology,the proposed architecture improves the overall area-time efficiency compared with state-of-art works.Based on layered normalized min-sum algorithm,a partial parallel LDPC decoder is designed for(8176,7154)code,which is adopted in Consultative Committee for Space Data Systems for near-space communication.The proposed decoder is implemented in Xilinx Kintex-7 FPGA board.Key technologies such as paralleled pipeline structure,optimization of the variable node updating process and division of sub-matrix are used in the design of the proposed decoder.The proposed decoder achieves 1.638 Gbps throughput with a clock frequency of 95 MHz,and 38213 slices are used in total.