The Design Of AXI Bus Monitor For Post-silicon Verification

Post-silicon verification has become one of the most important parts in contemporary large-scale integrated circuit silicon verification.However,in the post-silicon verification,the observability and controllability of the internal logic signals of the silicon chip are extremely poor.During the running of a silicon chip,only a small amount of internal information of the silicon chip can be observed through the limited chip pins,which brings great difficulties to post-silicon verification.However,the market has higher requirements for integrated circuit products' design time,products' performance and stability,and there is an urgent need for efficient methods to debug and locate system faults and analyze system performance bottlenecks.The AXI bus has the performance advantage of high bandwidth and is widely used for on-chip data transmission.At the same time,the AXI bus' s complex interface and hundreds of thousands of signals make it difficult to observe its status on the silicon chip.This paper designs and implements the AXI bus monitor,which provides post-silicon verifiers with more AXI bus information in the silicon,which makes post-silicon verification more intuitive and more efficient in fault location.The main work of this paper is as follows:Firstly,it realized the integration of the three functions of AXI bus transaction tracking,performance monitoring and active error reporting.According to the fuzzy value of the partial signal of the AXI bus signals,other signal values of AXI transactions can be tracked and recorded.Besides,it can also perform statistics on the bus performance.In addition,when it is detected that the response of a transaction is an error,or the returned response is not received over time,it will actively record and report the interrupt.Secondly,the time-sharing monitoring of multiple AXI buses is realized in the design.At the same time,through the selection of high-bit wide data bus signals and other signals,it meets the needs of monitoring more bus information while reducing hardware costs and increasing using efficiency of debugging resources.Finally,on the basis of register-transfer level code completion,a verification platform based on UVM methodology was built.By writing a behavior-level reference model that with the same function like the design,the automatic comparison of the verification data is realized,which reduces the verification workload and reduces the probability of manual inspection errors.The final verification results show that the statistical values of code coverage and function coverage have reached 100%,which guarantees the reliability of the design.The design described in this paper implements the functions of transaction tracking,performance statistics,and error interrupt reporting.It is suitable for a variety of signal widths,cross-clock domain AXI3 and AXI4 protocol bus monitoring scenarios,and has good scalability and reusability.The AXI bus monitor designed and implemented in this paper has been integrated into a company's processor chip to monitor multiple AXI buses on-chip,and waits for further testing after tape-out.