| The integration and the design complexity of the high performance processor are growing higher.However,due to the slow simulation speed and inaccurately electrical model,the pre-silicon verification cannot find all the bugs before tape-out.Therefore,the post-silicon verification technology turns to be more and more important.But the post-silicon debugging is very difficult and time-consuming,so more and more researchers are devoted into this area.Today,the high performance processor design comes to the many-core architecture,which also faces the same threats in the verification and debugging area.What's more,many-core processor verification and debug are facing more challenges because many-core designs are more complex and have more state corners and working modes.To improve the post-silicon debugging performance in the many-core processors,this paper studies the problems in post-silicon debugging,such as metastability in cross-domain-coverting,DRAM decay when clock stall and various memory access delay,and proposes a deterministic execution method.Based on this method,this paper proposes a NoC-based many-core processor debug architecture and implements all the necessary components in this architecture.This paper also proposes the methods to enhance the observability and controllability of the processor silicon chip,such as IO adaptor supporting single-step debug,post-silicon bug mask technology.The main contributions of the paper are summarized as following:(1)A NoC-based many-core processor debugging system architecture for deterministic post-silicon verification has been proposed.The basic reason for the difficulty of the post-silicon debug is the weak observability and controllability,and the method by using on chip trace capture,such as DFD(Design for debug)technology,can enhance the observability of the internal status of the silicon chip,but the improvement cannot satisfy the need of the fast location in the debug process,or it would consume too many hardware resources.By using the deterministic and the single-step execution characters of the post-silicon platform,it can significantly reduce the hardware requirements for the debug components,and provides better observability.Therefore,based on the deterministic single-step implementation theory,this paper proposes a debug system framework based on the NoC(Network on Chip)technology for many-core processor based on the characteristics of many-core processor.The support technologies for the framework are briefly designed,including hardware queue-based fast bug detection,signal trace capturing based on distributed low hardware overhead embedded logic analyzer,software trace capturing based on deterministic execution and checkpoint mechanism,delay balanced cross-trigger signal network and high-precision timing signal network.In order to verify the feasibility of this architecture scheme,an enhanced verification platform based on the self-owned processor is proposed.The experimental results show that the proposed post-silicon debugging system accounts for about 0.39% of the total chip resources,and the function of each supporting component has reached the expectation effect.(2)A deterministic single-step debug system design method for many-core processor post-silicon verification has been proposed.The key factors affecting deterministic single-step debug of the post-silicon verification system are threefold: uncertain transmission delay for signals in clock domain crossing caused by metastability,non-determinism due to the clock stall in single-step debug process,and the DRAM contents loss and the uncertain memory access latency during the clock stalls.Inspired by the recent research development on the deterministic transmission of the clock domain crossing signals,the paper gives a brief discussion on the latter two problems.First,the basic theory of deterministic execution of post-silicon chip is detailedly analyzed.Then,based on the deterministic transmission theory,a brief theoretical analysis and the solution are proposed to solve the non-determinism problem during the clock stall process.Thirdly,the design method of deterministic single-step debug memory controller based on delay prediction mechanism is proposed for the problem that the DRAM contents are lost and the memory access latency is uncertain in the case of the clock stalls.Experimental results on the FPGA platform show that the additional area for this method does not exceed 0.36% of the total chip logics,and the average performance of the system is only reduced by 1.60%.The deterministic single-step debug post-silicon verification system is based on the proposed innovation,which is the foundation of the aforementioned many-core processor debug system framework.After the post-silicon verification system owns a good controllability,and with the cooperation of the aforementioned debug components and scanning-based debug,the whole required contents can be time division obtained by executing the same stimulus multiple-time,which significantly reduces the hardware overhead.(3)A high-speed serial interface adapter supporting single-step debugging is proposed.In the post-silicon debugging process,the hardware emulator is an important assistant tool to debug the post-silicon bugs.However,the existing hardware emulators cannot support the single-step debugging function when the high-speed serial interface IO devices are connected.As a result,the function of the hardware emulators cannot be effectively utilized while debugging the IO-related bugs in post-silicon chip.In this paper,a high-speed serial interface adapter design method is proposed to support single-step debugging.To resolve the problem that the delay of the high-speed IO channel in the simulator is inaccurate,a compensation method for the adapter is proposed.Experimental results based on the FPGA platform show that the designed adapter can effectively maintain the connection state with the real equipment during the process of the emulator stall,and the simulation results of the system IO performance are closer to the real equipment under the appropriate delay compensation configuration.(4)Two methods for post-silicon bug mask are proposed.The located post-silicon bugs would disrupt the normal execution of the partial verification stimulus,which may cause other silicon bugs to be hidden and escaped to the next silicon tape-out stage.In order to solve this problem,this paper designs and implements the method of processor state backup and recovery.Based on the deterministic characteristics of the post-silicon verification platform,this paper presents a bug mask method.Firstly,the hardware emulator is used to obtain the correct state of the system after the bug is repaired.Then,the fault state of the silicon chip is covered by the correct state of the hardware emulator when the bugs happen in the silicon chip,which realize the goal that the bug is masked.In addition,for the realistic application environment,this paper proposes another method of on-line masking partial post-silicon bugs by controlling the data flow,which is mainly applied to bugs mask in the logic components other than the processor core,such as the IOs.Experimental results based on the FPGA platform show that the above two methods can effectively mask the bug for a logical bug in the DMA controller,and the data bandwidth loss caused by the flow control method does not exceed 2.5%. |
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