A Monitoring System For SoC Chip Performance Analysis In Pre-silicon Verification

With the continuous development of mobile communication technology,the speed of updating mobile communication devices is getting faster and faster.Consumers choose a product that is not limited to the basic functions of the product anymore,and will also pay attention to the performance and the power of the product to a large extent.How to maximize the performance of the chip and reduce the power consumption of the chip in the limited project cycle,based on the guaranteed normal function of the So C chip,is a big challenge for chip developers.In order to cope with this challenge,the industry has introduced various methodologies such as UVM for the verification of pre-silicon functions and introduced various verification methods and means such as dynamic simulation,static inspection and hardware acceleration.For pre-silicon power analysis,EDA vendors have also released PTPX which is used to evaluate the power consumption of netlist,and Power Artist which is used to evaluate the power consumption of RTL.However,for the pre-silicon performance analysis,there is no standard process and special EDA tools in the industry,and there is no unified index to quantify the performance of the So C chip and the goals to be achieved,and there is no effective performance analysis and optimization solution.In this paper,a solution for pre-silicon performance analysis and optimization is firstly proposed based on a research on the architecture and the data path of a mobile baseband So C chip.Then this paper analyzes the structure of the LPDDR4 controller,introduces the AXI protocol and puts forward a series of performance index,which is used to quantify the transmission performance of the RTL and a performance target,which should be reached after the design parameters of So C chip has been optimized.After that,an online monitoring system VIP named P2P(Performance Tool for Pre-silicon),which can online calculate out the performance index of the RTL during the RTL simulation,is developed based on UVM and System Verilog language and is integrated into DDR module level and So C level verification enviroment separately in this paper.Finally,this paper analyzes the performance report from P2 P during RTL simulation of performance stimulus scenarios in different design parameters' value,and locates the root cause of a design bottleneck which restricts the perormance of So C chip,and optimizes the design parameters which affects the So C chip's peroformance based on the solution proposed in this paper after the DDR module level and So C level peroformance testcases are ready.After comparing the evaluation results on So C chip's performance before and after performance optimization,it was found that the average throughput index of the performance scenario in which the Master4 solely initiated the data write-only access to the DDR memory device in So C chip was increased by 144.27%,and the average throughput index of performance scenario in which the Master4 solely initiated the data read-only access to the DDR memory device in So C chip was increased by 139.18%.It can be concluded that the pre-silicon real-time performance monitoring system P2 P can achieve the expected design goals.P2 P can calculate out the performance index of RTL during dynamic simulation to quantify the transmission performance of the RTL.And after design iteration and performance optimization based on P2 P,the performance index of the So C chip can achieve the target and tends to converge before tapeout,thereby reducing the risk of tapeout.