Design Of Composite Data Terminal Based On Nios ? Processor

With the development of satellite receiver data terminal towards multi protocol and multi-channel,miniaturization of satellite receiver data terminal for multi application has become the development trend in the future.However,the traditional data terminal based on MCU,ram or special chip to expand the number of channels has been difficult to meet the diversified functional requirements of the data terminal in the information age due to its poor timeliness,portability and scalability.To solve the above problems,this paper develops a composite data terminal based on Nios ? processor.In order to meet the needs of Beidou satellite navigation system miniaturization and multi application receiver,the composite data terminal based on Nios ? processor uses Intel cyclone 10 FPGA as the core chip under the quartus prime development platform to realize multi-channel serial port,can port and Ethernet communication by building a multi soft core processor system.The specific work includes:(1)Research on multi processor systemTo solve the problem of low efficiency of single processor system task execution,the data terminal uses four Nios ? processors as CPU,one Nios ? as main processor,and the other three are serial port,can port and Ethernet subsystem coprocessor.Four processors work together to complete the multi protocol data terminal communication task.And the hardware circuit of the system is designed.(2)Research on address allocation method of shared RAMIn order to solve the problem of instruction execution disorder in multi-core processors,the running space of instructions in multi-core processors is realized by sharing ram on chip.In this paper,the shared RAM address segmentation technology is used to effectively solve the problem of RAM address overlapping of processors.(3)Research on topology of programmable BridgeAiming at the problem of high consumption of programmable I/O interface in multi-channel communication,a bridge topology is established to realize the communication between coprocessor and main processor and greatly reduce the consumption of programmable I/O.The network clock is isolated by logic bridge.(4)Research on soft core of CAN controller and software implementation of simple socket serverAiming at the problem of complex circuit structure and power consumption sensitivity,can controller is realized by writing state machine and customizing SJA1000 compatible soft core.In order to establish the TCP/IP communication between the board and PC,this paper designs a software scheme based on simple socket server.(5)Research on timing constraints of RGM? complex clock treeAiming at the complex clock tree of RGM? communication,this paper adopts timing constraint to ensure the timing convergence and get the correct timing analysis report on the basis of increasing the maximum working frequency.In order to verify the correctness and practicability of the design,the digital simulation of Modelsim platform is used to verify the correctness of each module function.Then the board level test models of serial port,can port and Ethernet subsystem are established respectively.The test results show that the communication indexes of this design meet the design requirements and have certain practical application value.