Design Of Settling Time Minimization For CMOS Three-stage Operational Amplifiers

Operational amplifiers are the basic building blocks in the various analog and mixed-signal circuits and systems and play important role for the working of the entire system.The rapid development of process technology and the continuous reduction of the feature size of devices have always brought about difficulties to the design of operational amplifiers.As a consequence,a variety of new amplifier structures have emerged to meet such challenges.This thesis concerns about the design for the settling time minimization of CMOS three-stage operational amplifiers.Due to the reduction of the supply voltage of short-channel devices,the intrinsic gain of the MOS transistor is reduced and the usual two-stage structure is unable to meet the gain requirement of the amplifier.On the other hand,the high gain cascode structure is also not suitable in the low voltage circumstances since the limitation of the smaller voltage swing.The three-stage cascaded structure is therefore widely adopted in modern technology since its simultaneous fulfillment of high gain and high swing requirements.The traditional design of three-stage operational amplifier usually takes bandwidth and phase margin as the performance objective,while in many discrete system applications such as SC(switching capacitor)circuits and A/D converters,what is really needed is the time-domain performance of settling time.The design methods of time minimization existed in the literature are all based on the approximate transfer function model.The design results so obtained are inaccurate.A design method for the exact settling time minimization of three-stage CMOS amplifiers is presented in this thesis.Under the given settling time accuracy,this approach finds the accurate solution of the design parameters from the equations established based on the time minimization condition for the exact closed-loop step response of the amplifier through the Newton's method.Starting from the approximate design results obtained using the transfer function method,the Newton iteration is converged within a few numbers.Since the time domain response in the entire solution process is simulated by the HSPICE simulation,the error existed in previous methods is eliminated and the design result is obtained at SPICE-accuracy.The tedious manual tuning in the circuit design phase is thus avoided.A number of three-stage amplifier designs with the NMC,NMCR structures are carried out and the results demonstrate the effectiveness of the method.The influence of the process parameter fluctuation is finally discussed in the thesis.Comparing with the approximate third-order transfer function method,the Monte Carlo analysis for the settling time of the design obtained by the proposed method shows both smaller maximum and average value.A worst case design method for the minimization of the settling time is further given and validated by illustrative examples.