Research And Design Of Continuous-time ?-? ADC For TD-SCDMA/LTE Standards

Nowadays,the fast evolution of new wireless communication technologies and the huge number of old technologies' subscribers make a long-term coexistence of multi-standard and multi-mode wireless communication technologies.Thus,multi-mode RF?Radio Frequency?transceiver is of great significance and has broad market prospects.As a critical block in multi-mode transceivers,multi-mode ADC?Analog-to-Digital Converter?is confronted with new difficulties: on the one hand,the larger signal bandwidth of new technologies brings about new challenges on the speed and resolution of the ADC;on the other hand,the MIMO mode of LTE system makes the requirement on power-efficient and low-cost more stringent.Therefore,high performance,low-power,and low-cost multi-mode ADC has become a hot research topic in multi-mode RF transceivers in recent years.This dissertation mainly focuses on research and design of power-efficient,low-cost,multi-mode continuous-time ?-? ADC for TD-SCDMA/TD-LTE digital receiver.It proposed a 3rd-order single-loop feedback structure ?-? ADC,which is directly coupled to the output of the mixer.To improve the noise compression the ADC,a 4-stage operational amplifier with novel frequency compensation technique is proposed.And then an ultra-low power overload recover circuit is proposed to overcome the overload recovery problem of a feedback ?-? ADC.And a RC constant and a DC offset automatically calibration methods and circuits are proposed also.And finally,a low-power low-cost continuous-time ?-? ADC for TD-SCDMA/TD-LTE system was designed,taped out and measured.The specific research contributions of this work include:1.A 3^rd-order single-loop feedback continuous-time ?-? ADC is proposed.The ADC is directly coupled to the mixer's output,thus the channel selection filter in the RX chain was removed and the power dissipation and active area are reduced efficiently.The co-efficient of the proposed ?-? ADC is re-configurable,thus the ADC can work in two different modes?LB mode and HB mode?to meet the requirement of all the 7 signal bandwidths of TD-SCDMA and TD-LTE standards.2.A 4-stage operational amplifier,which adopts both feedforward Gm-C and Miller compensation techniques,is proposed.Measurement results show that the in-band?0-10MHz?gain of the proposed amplifier is improved over 6d B comparing with a classical 2-stage amplifier with same bandwidth.Therefore,the noise suppression of NTF is improved efficiently.3.To overcome the overload recovery problem of feed-back ?-? ADC,an ultra low-power,low-cost overload automatically recovery circuit is proposed.4.An automatic RC constant calibration block is adopted to minimize the co-efficient variation due to CMOS process.And an automatic DC offset calibration block is applied to the design to eliminate the influence of DC offset in ZIF receiver.Furthermore,a novel ultra low-power voltage detector,as well as digital control logic,is proposed to enable the calibrations during power-on sequence of the chip,then store the calibration results and shut-down the calibration blocks when the calibrations are done.In this way,all the calibration blocks don't consume any additional power during receive slot.The proposed ADC is designed and taped out in IBM 0.13?m CMOS technology.Test results indicate that this design achieves 72 d B to 84.3d B DR,69.2d B to 82.9d B peak SNDR and-78 d B IM3 over a 0.7MHz to 10 MHz baseband signal bandwidth?1.4MHz to 20 MHz radio frequency signal bandwidth?.The proposed ?-? modulation occupies only 0.2mm2 active area,and consumes 6.41 m W and 8.31 m W under 1.5V power supply in LB and HB,respectively.All the performances of the design meet the commercial requirements of a TD-SCDMA/TD-LTE mobile terminal,and the design has been applied to commercial 4G data card products successfully.