Hardware Design And Implementation Of QC-LDPC Code Based On FPGA

Since the beginning of the1990s, LDPC code again aroused people’s attention for its performance approximate to the Shannon limit. LDPC code is being applied in a wide range of fields, such as in DVB-S2, CMMB,4G communication systems, satellite communication and digital watermarking system. Currently, for more and more pre-research projects in the field of aerospace, the scientists are demonstrating the feasibility of LDPC code in improving system performance.It is a complex task for the optimal design of LDPC code, each optimized code needs to simulate to assess its performance. In many scenarios, there is a high requirement for the error floor of LDPC code. Generally, the simulation needs to achieve bellow10-7bit error rate, and therefore the amount of data in the simulation has to reach at least109bits. Software simulation will require a lot of computing time for such a large amount of data. The paper attempts to design a hardware emulator for quasi-cyclic LDPC based on FPGA platform, which can realize assessing the performance of simulation for some certain LDPC code in a very short time.In order to implement the design of LDPC code emulator, the paper mainly has done the following work. First, it will introduce the encoding algorithm, and present a called SRAA encoding circuit design and its principal based on the quasi-cyclic generation matrix. And then focusing on another quasi-cyclic parity check matrix, describes its encoding algorithm by using the quasi-cyclic characteristics and its dual-diagonal structure, which deduces the iterative equation of parity bits and then can be implemented on the FPGA hardware platform. The encoding delay is shorter, so it can achieve a high throughput. Secondly, research and compare the performance of some kinds of different decoding algorithm, iterative convergence speed and its implementation. And focusing on the architecture-aware QC-LDPC code, it will discuss its layered decoding algorithm and implement universal decoders based on the algorithm on FPGA platform. At last, after completing the design of peripheral modules, such as random data source module, the mapping module, soft demodulation module, AWGN(additive white Gaussian noise) and bit error statistics module, together with QC-LDPC encoder and decoder, all the modules are combined into a called QC-LDPC code hardware emulator. Once established, the emulator configured by different check matrix parameters and noise variance can easily achieve a fast simulation of a large amount of data.