High-speed Design And FPGA Implementation Of LDPC Encoder And Decoder For 5G Standard

With the advent of 5G commercial era,5G mobile communication technology unlocks new intelligent business scenarios such as smart city and unmanned driving for users with its features of high data rate,low transmission delay,and large connection density.But higher requirements for key technologies such as channel coding are put forward at the same time.LDPC code has been adopted as the coding scheme for data channel in 5G e MBB scenario due to its near-Shannon limit performance and decoding algorithm with linear complexity.Based on the background,it is of practical significance to study the high-speed hardware implementation of 5G LDPC encoder and decoder.In this thesis,the encoder is designed according to the dual-diagonal and diagonal structure of the parity-check matrix of 5G LDPC code.And it is determined that the parallelism of the encoder is the lifting size according to the quasi-cyclic structure of QC-LDPC code.The parity bits are generated only by cyclic permutation and XOR operation,which simplifies the circuit design.The capacity of memory and the quantization bit width are designed according to the information corresponding to the LDPC code with the maximum length to support all code lengths and rates in the 5G standard.The permutation network adopts the QSN architecture to support 51 different lifting sizes.The encoder can achieve a clock frequency of 240 MHz on the Xilinx FPGA platform Virtex Ultra Scale+ VCU118(chip:xcvu9p)and the throughput is up to 15.717 Gbps.The encoder consumes few hardware resources,with LUT,FF,and BRAM accounting for only 0.60%,0.28%,and 1.48% of the available on-chip resources respectively.In this thesis,the layered offset min-sum algorithm is used in the decoder according to the simulation performance under different parameters,which can be simply implemented by addition and comparison operations.The decoder is designed based on the block-parallel architecture which can achieve a good compromise between throughput and resource consumption.In addition,an optimization strategy is proposed to improve the decoding throughput by rearranging the reading order of messages corresponding to the CPM in each layer.The strategy can reduce the idle cycles introduced by change of row weight and memory access conflicts in the layered decoding without loss of decoding performance.The decoder is flexibly compatible with LDPC codes of all code lengths and rates in the 5G standard and supports frame-by-frame configuration of code parameters.It can achieve a clock frequency of 150 MHz on the Xilinx FPGA platform Virtex Ultra Scale+ VCU118(chip:xcvu9p),and the information throughput can reach up to 397.990 Mbps with 25 iterations.The LUT,FF,and BRAM consumed in the decoder occupy 8.89%,2.25%,and 8.10% of the available on-chip resources respectively.Finally,the on-chip verification of the encoder and decoder is completed,and the decoding performance is tested based on the FPGA-PC simulation platform.The simulation platform can flexibly configure the code information and simulation parameters.In this thesis,71 LDPC codes in the 5G standard with different code lengths and rates are randomly selected and tested.The results show that the performance gap between FPGA simulation and floating-point SPA is within 0.3d B for moderate to high code rates and within 0.5d B for low code rates.