The Design And Implementation Of Cache Based On AMBA Bus

With the continuous development of the level of science and technology,the continuous progress of semiconductor process manufacturing technology,the integration and complexity of chips are getting higher and higher,which makes the design cycle and design cost significantly increase.In this context,System on Chip(SoC),which has the characteristics of good portability,short design cycle,and low design cost,has been widely used.SoC technology has developed rapidly.The high-speed central processing unit(CPU)in the SoC chip serves as the "brain"of the SoC chip,and its performance has also been significantly improved.,DRAM)performance is difficult to improve to the same level as the CPU,which greatly limits the role of high-performance CPU.To solve this problem,Cache came into being.Cache uses Static Random Access Memory(SRAM)as the storage unit.SRAM is expensive and large in area,so it cannot be used as main memory.Using SRAM to form a Cache connection between the CPU and main memory can alleviate the problem of performance imbalance and make the CPU play a better role.This article mainly introduces the design and implementation of Cache in SOC chip.First,the AMBA bus principle and Cache principle are analyzed in detail.Then complete the design plan,and use Verilog to complete the design of Cache RTL.The designed Cache supports automatic and manual power-on requests and SRAM failure requests,which is convenient for selecting configuration when used in different environments;supports instruction prefetching,which can reduce latency and power consumption for CPU access;supports Cache hits Count and count Cache misses;support error state interruption;support Cache size configuration,which can configure different Cache sizes according to the project to improve the reusability of the Cache module.After the design is completed,integrate the Cache module into the SoC system and write verification codes to verify different functions;perform post-simulation after synthesis and placement and routing are completed;then use the FPGA development board to connect the simulator to the Cache module for FPGA verification;pass FPGA After verification,tape-out was performed,and after tape-out,the Cache module in the finished chip was tested.After the verification work in multiple stages is completed,the designed Cache module meets the expected requirements of the project,with a hit rate of 99%,shortening the CPU access time by 70%,and reducing the overall power consumption of the chip by 13%.And the project involved in this design has been successfully taped out.It can improve the access performance of the CPU and improve work efficiency.