Design Of SRAM In L1 Instruction Cache For 32-BIT Microprocessor

With the increasement of integrated scale of processor, the capacity of cache based on Static Random Access Memory (SRAM) technology is rapidly increasing and the proportion of its area in System on Chip (SoC) is increasing year by year, thus the performance of cache has a significant impact on the performance of Central Processing Unit (CPU). The main application of cache is to smooth the speed difference between processor and off-chip memory, therefore SRAM is typically used for the design of cache in order to obtain higher access speed and the custom design of high-speed low-power SRAM is very favorable for the improvement of CPU performance.Firstly, by analyzing read and write operations of SRAM memory cell, this thesis obtains the limits of transistors in storage unit and provides the specific size of the memory cell used in the SRAMs. In order to shorten the pulse width of wordline and reduce the power consumption of bitline during read and write operations, self-time technique is adopted to control the read and write operations of Data SRAM. Then, this thesis introduces a novel latch type sense amplifier which can improve the speed of Data SRAM and reduce the power consumption during read operation as well as a np-CMOS dynamic Tag comparator which can effectively accelerate the speed of comparison of Tags by separating the upper address and the lower address. Then, the layout design of L1 instruction cache is introduced in this thesis and the overall layout of SRAM is provided as well. Finally, a simulation of read and write operations is conducted to verify the functional correctness and timing compliance of the SRAMs.The capacity of Data SRAM, Tag SRAM and Status SRAM designed in this thesis are respectively 32KB,3KB and 128B. At 1.0V supply voltage, the simulation results based on TSMC 65nm process show that the maximum read or write delay of Tag SRAM, Status SRAM and Data SRAM is 0.479ns meeting the design requirements of 0.5ns. In addition, the operating frequency of SRAM is up to 1.33GHz which provides 30% improvement compared with the design requirements of 1GHz. Simulation results in 1GHz clock frequency show that the power consumption of Data SRAM is 14.67mW and the overall power consumption of Tag SRAM and Status SRAM is 48.64mW, both meeting the design requirements.