Design And Implication Of Instruction Cache Data Array

With the advancements in the fabrication process and the increasing complexity of logic designs, the memory is becoming the main bottle-neck of the processor's frequency. So, it is becoming an important part of designing a high speed and low power memorizer for the processor. Now we attach more and more important to it's study.Using the method of Full-Custom design, this paper design and implement a 16.5 KB Instruction Cache Data Array, in 0.13μm CMOS process, whose work frequency is 1GHz and have implemented the layout design and verification. Based on this design, this paper having given the method of creating LEF views, and simulation verification after layout, as well as the method of creating timing model and the method of inserting BIST circuit automatically. Firstly, after finishing the layout, we using the interface of which was provided by tools as Nanosim/Xa, etc, to simulation and verification Secondly, we have to provide the LEF view and .lib timing model, for floorplan and static timing analysis in later work. Finally, we have to test our design because there may be some fault in fabrication. MBISTArchitect tool can provide some test arithmetics. For each test arithmetic, there are some corresponding faults. It can generate different BIST circuit/control circuit/test-bench/synthesis scripts and so on, using this generated files, the test circuit can be easily achieved.In the typical case, when the input slew is 44ps and output load is 0.1706pf, the delay of writing data in SRAM is less than 720ps and the delay of reading data is less than 770ps. Under the condition of 1GHz , the average power consumption is less than 50mw , and the area is 1021504.256um~2, achiving the design request.