Cache Optimizations Based On The Timing Speculation SRAM With Near Threshold Voltages

As the number of integrated transistors in modern processors continues to increase,further improvements in processor performance are increasingly limited by the conflict between power consumption and heat dissipation.On the other hand,how to minimize the energy consumption while meeting the performance requirements for battery-powered mobile terminal applications and Io T applications,which are more sensitive to energy consumption,has become the first challenge for designers.To further reduce the energy consumption of the system,industries and academia have extended the operating voltage to the near-threshold range.However,at low voltages,the SRAM arrays,which make up the cache of the system,have a high probability of timing errors that can greatly affect the performance of the entire system.Timing speculation scheme can detect the timing errors by sensing the data twice and correct it by extending the bitline discharging.We proposed a Timing Speculation Cache: TS Cache that directly built by using the CS-SRAM array without any optimization,which can detect and correct the timing errors.However,its system performance will be degraded because of the extended bitline discharging.Hence,we proposed two micro-architectural optimizations based on the TS Cache,where the new cache is called as Reuse-aware Remapping timing Speculation Cache(RRS Cache),to alleviate the influences brought by timing errors under the near-threshold voltage.One of two optimizations in RRS Cache: Cacheline Remapping scheme can group timing errors into fewer Cachelines to decrease the ratio of the Cacheline with timing error.Moreover,the other optimization: Reuse-aware Cache filling/replacement policy prefer to allocate the strong(without any timing error)resource to the data that has high probability to be reused by the read request,which can further decrease the probability that a read request encountering timing errors.To evaluate the performance impact of RRS caches,we compared 8 cache designs in terms of performace,area,energy,et cl.Compared with TS Cache,the power consumption and the additional area consumption of the L1 RRS Cache are improved by 0.2% and 1.76% respectively,with 9.8% decrease of the average access latency;as for the L2 RRS Cache,the power consumption is reduced by 13.5%,and the additional consumption area is only 2.54%,its average access latency is also reduced by 9.4%;the performance of the whole system(using Cycle Per Instruction to compare,CPI)is increased by 9.8%,which reachs 98.6% of the ideal cache design(the design that assumed to have no timing error)and also is the best one in the other seven designs.