Design And System-level Verification Of Instruction CACHE Architure

CACHE has been an important functional component to enhance the system performance of high performance microprocessor. Its size and speed have been a main criterion to evalue the characteristic of microprocessors. According to the requests of the general microprocessor system design, the paper realizes the design of TLB and the body of instruction CACHE based on thorough research of the CACHE technology.This paper has proposed and implemented a kind of high-efficient CACHE structure. It realizes the instruction reading per cycle under the TLB hit condition. In order to speed up the address transformation of TLB, we have carefully designed the precharge logic of CAM reading, the sensitive amplifying ones of CAM driving and the Domino dynamic logic of SRAM reading. The performance of each component is greatly improved by the applications of these logics and structures. Further, we have designed the parallel mode between CACHE and TLB at the structural level that results in instruction read-out in the single cycle. That is, while TLB carries on the address translation, CACHE is reading out the address and the data to the specific buffer.In addition, we have designed the interface buses and debugging structures, and have increased debugging structure channels in order to improving the electric circuit testability.Moreover, the utilizations of the functional component channel design and the testable design have carried on the detailed single chip system-level verification of the instruction CACHE component.After tape-out actually, sample chips can in the single cycle realize the instruction reading under 0.18μm CMOS process and the 250MHz operating frequency.