Research And Implementation Of Low Voltage SRAM Storage Circuit In MCU

Demand for energy-efficient microcontroller units applied to Internet of Things(Io T)sensor nodes has grown significantly.In order to achieve the next generation of Io T systems based on intelligent sensor node applications,the development of low-power and high-performance microcontrollers is important.The energy consumption of the microcontroller mainly comes from the static leakage power of the scratchpad memory and the dynamic power of the instruction cache in working mode.Therefore,effectively reducing the power consumption of the scratchpad memory and the instruction cache becomes the key to the low-power design of the microcontroller.For scratchpad memory,a yield optimization scheme based on dual power supply strategy is adoptted in order to improve its yield at low voltage,firstly.Secondly,an extrem data retention voltage compression method is used,which effectively reduces the leakage power consumption of the memory in sleep mode and shutdown mode.For instruction cache,a read-write detection type zero-level cache scheme is adoptted to reduce the dynamic power,which refresh specific zero-level cache blocks by detecting the working status of the instruction cache.In addition,according to the requirements of the microcontroller system,a parallel access instruction cache scheme and a serial access instruction cache scheme based on the read-write detection zero-level cache is developed.Finally,in order to further improve the hit rate of read block in zero-level,a high width data cache scheme is used.Finally,the scratchpad memory(4KB)and instruction cache is taped out using TSMC40 nm ULP process.The chip test results show that the scratchpad memory can work normally at a minimum operating voltage of 0.7V;and the static leakage current in sleep mode is 14 n A@0.9V?TT corner?25?,which is 88.6% lower than the commercial memory.Therefore,the aggressive data retention voltage compression scheme effectively reduces the leakage power of scratchpad memory.Meanwhile,the post-simulation results of the instruction cache show that the power consumption benefit of the parallel access cache and the serial access cache is 50.7% and 71.7%,respectively;and Power Delay Product has decresed 69% and 75%,respectively.Therefore,the read-write detection zero-level cache scheme can effectively reduce the dynamic power of instruction cache.