Research And Implementation Of Performance Testing System For High-speed Analog-to-digital Converters

Analog-to-digital converters are being used in radar,wireless communication systems,software-defined radio and so on as the key devices of analog-digital mixed-signal processing.Bandwidth and sampling frequency of the ADCs used in radar and communication systems are becoming higher and higher,meanwhile ADC interfaces are being developed from parallel ports to high-speed serial ports such as JESD204 B and JESD204 C,which dramatically increases the difficulty of ADCs performance test,evaluation and verification.It is difficult to meet the demand of newest ADCs performance test for the traditional performance testing systems which have the drawbacks of lack of high-speed serial ports support,inadequate data storage and low transmission rate.In order to meet the requirements in high-speed ADCs performance evaluation,research and development of the ADC chips and application development,it is urgent to design and implement performance testing system for high-speed ADCs.Firstly,on the basis of research on ADC performance parameters and testing methods,requirements of a general testing system for ADC performance are analyzed,and then the architecture constructed of high-performance FPGA and DSP processor FMC daughter-mother card structure is proposed.In hardware circuit design while employing the TI's C66 x series DSP is used as the ADC test algorithms implementation module which takes full DSP's advantages of software programming convenience and super floating-point arithmetic capabilities to implement algorithm flow control and complicated digital signal processing.Meanwhile Xilinx Virtex-7series FPGA features in high operating clock frequency and variety of interfaces,which are utilized to fit for the ADC interfaces of CMOS,LVDS,JESD204 B and JESD204 C and to implement real-time parallel data preprocessing.By following FMC standard,the proposed hardware platform is separated from daughter cards with ADCs under test carried on,so that different ADC measurement evaluation can be carried out on a general hardware platform with just the standard ADC evaluation daughter cards re-designed,which improves universality and reusability of the proposed hardware platform.Then,based on the hardware platform of the proposed performance testing system for high-speed ADCs,the software design of the testing system is completed by means of top-down modularization.FPGA logic can implement the functions of data acquisition,data preprocessing,high-speed large-capacity data buffering and forwarding.Meanwhile the time domain and frequency domain analysis of samples are carried out in the DSP,and then the ADC performance measurement algorithms are called to complete the calculation of ADC performance parameters.DSP is also capable of transmitting measurement results to host computer through gigabit Ethernet and provide friendly operation interfaces.Finally,the experimental environment is built based on the designed testing system to verify the designed testing system.After testing the basic functions and performance of the proposed hardware platform,performance testing experiments are carried out on three ADCs under test with different types of interfaces,different sampling frequencies and sampling resolution to verify the reliability and validity of the designed ADC performance testing system.The experimental results show that the ADC performance testing system studied and implemented in this thesis can satisfy the demands of performance evaluation for ADCs interfacing via COMS,LVDS,JESD204 B or other interfaces,sampling frequency ranging from 240 MSPS to3200MSPS and the highest resolution of 16 bit,which has a certain engineering application value and reference significance.