Application And Research Of High Speed ADC Based On JESD204B Protocol

In the imaging equipment,communication,radar,industrial instrumentation and other real-time transmission of large amounts of data in the industry which requires its digital-analog converter sampling rate is getting higher and higer,more and more data bits,bandwidth,more and more wide,faster transmission speed.This high-speed data acquisition and transmission system put forward higher requirements.Most of traditional ADC uses the parallel bus for data transmission.With the increase of the sampling rate,the throughput of the parallel bus increases greatly,which increases the number of bits,taking up a large number of chip pins,making chip and PCB miniaturization difficult to achieve and in a large number of high-speed data signal alignment while controlling volage noise is difficult to do.Compared with the traditional parallel bus transmission ADC,the use of high-speed serial bus transmission ADC has a very obvious advantage,which requires a significant reduction in signal transmission lines,bus transmission rate is also significantly improved,and to improve the data transfer rate while saving wiring space,but also reduce the chip power consumption.The use of high-speed serial bus transmission of the ADC not only in the volume,power consumption and data transfer rate than the parallel bus transmission ADC advantage.In the high-speed data acquisition and transmission system serial bus transmission has become the future development trend.After studing the high-speed serial transmission technology,this paper designs the serial bus technology based on JESD204 B protocol and designs a high-speed ADC sampling circuit based on this protocol.The analog-to-digital conversion chip supports JESD204 B subclass1 working mode,connects with GTX interface of high-performance FPGA through FMC interface and receives AD sampling data,and finally transmits through PCIE cheat and PC.The main work of the paper is as follows:1.The application of JESD204 B protocol in high-speed ADC is analyzed,including the introduction of JESD204 B subclass,deterministic latency,link synchronization and JESD204 B IP core design.2.Design high-speed ADC sampling circuit,the circuit for the acquisition and transmission system is the key,respectively,form the analog front end,clock and power to be designed.3.Designed based on JESD204 B requirements of ultra-low jitter with dual PLL clock circuit.4.Study JESD204 B IP core in the mouth of the module function Xillinx's field programmable logic gate array chip XC7VX690 T to achieve its interface protocol.5.The system uses a high-speed ADC FMC acquisitionplatform + FPGA master data reception architecture,the architecture for high-speed ADC FMC acquisition card for FMC-based specifications of the various data receiving master,flexible and convenient test.6.Design a low power,high efficiency,ultra low dropout linear power from the overall power consumption of the system.7.Finally,the signal-to-noise ratio,effective bit number and spurious dynamic range(SFDR)of high-speed ADC are analyzed respectively.The test results show that the high-speed ADC acquisition system based on JESD204 B protocol is excellent in performance and stable and reliable.