Research And Design Of DDR3 Memory Controller Based On FPGA

Memory is an important part of computer system, as all the orders and data can only be processed unless loading into memory. Access request by processor can’t be directly identified by memory, so memory controller is used to implement the controlling of memory. The controller determines many important parameters of the computer system such as the memory capacity, the number of storage stacks, type and speed of memory and the depth and width of data. Therefore, memory controller acts as one of the key factors to the performance of memory or even the whole computer system, and research related to it becomes hotspot in fields of high-performance computing and embedded system.First, the paper introduces storage wall, the problem which restricts the performance of computer, and the current situation of memory controller. Then, detailed description of new features, low-power dissipation and design technique of DDR3 are presented. Working principles, basic operation of DDR3 and the standard of JESD79-3E_DDR3 are studied, some significant parameters which affect design function and property are extracted. All these provide theory support for the design of memory controller. Further, on the basis of the external controller solution of Altera and features of embedded system, the paper demonstrates the designing scheme and works out the overall structure of the IP core of memory controller, which is divided into transport and physical layer. Then, based on the design idea of top-down, the transport layer is analyzed in detail by being divided into submodules. Verilog HDL is adopted to perform programming to modules, including initialization, user interface, abiter, error checking and correcting and command producing module. To design the physical layer, the IP core-ALTMEMPHY-of Altera is called to complete the butt joint with controlling logic by generating interface.After devising the IP core of the controller, the paper uses Verilog HDL to program the Test Bench, and executes simulation to the IP core in Quartus 10.0 and Modelsim. Then, simulation results of the key modules such as user interface, initialization and abiter are presented and analyzed. In the end, the paper proceeds FPGA verification to the IP core of the controller based on the development board of Altera Stratix IVE, when a single carrier signal serves as a test vector, the logic analyzer Signal Tap is used to finish the signal sampling to output test points, and MATLAB is used to restore the sampled data and compare it to the input. The comparison shows that the restored and input signals are just the same, demonstrating the paper completes simulation verification to major functions of the DDR3 controller. The memory controller designed in this paper can compatible with ALTMEMPHY digital interface-AFI, and have a good generality. This controller can detect and correct single bit of data errors and detect double bits of data error, the highest clock frequency of data transmission is 457.88 Mhz obtained by simulation. These shall provide references to the later design of DDR3 controller.