Research Of Implementing Viterbi Decoder Based On FPGA

In the recent years, with the improvement of technics of Large Scale Integration(LSI), people have made many progresses in research of Viterbi algorithm and its hardware realization. The Maximum Likelihood Decoder (MLD) algorithm and Viterbi algorithm are expatiated in this paper. After thorough study of Viterbi algorithm, the Survivor Memory and Decodeing Output (SMDO) is presented for improvement of performance. An analysis on the memory and delay has been made as well and the theoretic results indicate that the implementation of decoders with SMDO can save half amount that the old method needs memory and reduce (L-1) times decode delay. The simulation results also proof that the decoders have high rate and short delay.The Viterbi decoder base on our method has been designed by using advanced Field Programmable Gate Array (FPGA) devices. Firstly, this paper introduces the FLEX 10K devices of ALTERA and the MAX+PLUS II development tools. Secondly, the VHDL language are elaborated. Lastly, the paper traverse the implementation of the Viterbi decoder base on FPGA and SMDO method.In the design of the Viterbi decoder we consider the problems of its structure, restriction, decoding speed and memory space. At the same time, a testing for the designs has been completed in software and hardware. The results obtained from the simulation are consistent with theory.