A Study On Improving Flash Error Correction Performance Based On LDP Code

With the compression of flash memory process technology,the storage density and capacity of flash memory continue to expand,but the accompanying sacrifice is that its reliability is reduced.In order to ensure the reliability of flash memory,we must add error correction codes in the read and write process of flash memory.However,using traditional BCH error correction codes has been unable to meet the current memory error correction capability requirements.Low density partiy check code(LDPC)are beginning to be applied to storage error correction.When using LDPC codes for flash memory error correction.In order to read out more accurate data for error correction,we will use multiple threshold voltages for multiple reads,which will result in increased read latency of the flash memory.And LDPC code error correction ability intuitively depends on the size of the original error rate of the flash memory.The larger the RBER of the flash memory,the worse the error correction effect of the LDPC code.Therefore,in order to improve the read performance and error correction performance of flash memory,this thesis starts from two aspects.First,we consider to find a reasonable voltage layout scheme,with as few read voltages as possible and as simple as possible voltage layout scheme Possible accurate soft decision information.Secondly,we consider reducing the read operation of the flash memory by reducing the RBER of the flash memory,thereby improving the read performance and error correction performance of the flash memory.Through the research and analysis of the existing layout schemes,we find a voltage layout scheme that can be directly applied in a variety of distribution models,and combine the retention time and erasure times of flash memory,we get a table that selects the most suitable decoding scheme according to the RT.That is to say,we can directly look up the table through the current retention time of the flash memory and then select the appropriate voltage layout and number,and the upper limit of decoding iteration.Compared with the traditional voltage layout scheme determined according to the estimation,with this table,we can decode successfully through one read operation,instead of gradually increasing the number of voltages or improving the voltage layout after the decoding fails.In addition,this thesis also proposes a selective compression technology to reduce the RBER of the flash memory through compression,thereby improving the read performance of the flash memory and the error correction performance of the LDPC in the flash memory.The compression scheme proposed in this thesis comprehensively considers the selection of data pages and the determination of the compression ratio.Among them,the selection of data pages is mainly based on the frequency with which it is read.If the read frequency of a data page in flash memory is higher,the more likely it is selected for compression.Experimental results show that the selected compression scheme proposed in this thesis can bring an average 42% increase in read performance and an average 66% improvement in error correction performance without affecting the write performance and negligible overhead of flash memory.