Design And Implementation Of Mode Reconfigurable NAND Flash Error Correcting System

The parameter design method of error correction system in NAND flash memory has been deduced based on the characteristics and performance of NAND flash memory. Mode reconfigurable error correcting circuit is presented for NAND flash memory. This circuit can effectively avoid larger error bits than the designed error correcting bits. The8-bit parallel BCH codec algorithm circuit design method has been deduced based on traditional serial BCH codec algorithm circuit design method. Hereinafter, a circuit design method of parallel BCH code has been brought up, and a kind of BM iterative algorithm hardware implementation was deduced without finite field inverse operation. Based on the multiplexing technology of the codec algorithm circuit and combing pipeline technology with ping-pong operation technology, the performance of the correcting system is improved ingeniously while the cost increase was acceptable. The Modelsim software has been used to simulate and analysis the error correcting system after accomplishing the function design of the circuit. By the power analysis of the error correcting circuit, some methods have been used to reduce the power consumption of the circuit. The error correcting system circuit was implemented and tested in the Altera FPGAchip of the EP4CE15E22C8series. Under the same system operating frequency, eight times data throughput rate than traditional serial circuits was achieved with only double hardware cost. In comparison with traditional NAND flash error correcting circuit, the present error correcting circuit is relatively independent and portable. These characters enable it an applicable and promising error correcting circuit structure.46Figures,4tables,61references.