Research On Error Correction Strategy Optimization Of NAND Flash

With the reduction of chip manufacturing process technology and the emergence of 3D stacking technology,the storage density of NAND Flash chips is getting higher and higher,and the physical blocks are also getting larger and larger.At the same time,the raw error rate of NAND Flash is increasing sharply,and the lifetime of the chips greatly shortened,the data retention error in physical blocks and read disturbs are becoming more and more serious,which greatly affects the reliability of NAND Flash.BCH error correction code is an important way to ensure the reliability of SSD based on NAND Flash.However,as the raw error rate of the chip increases,the low-latency BCH code that meets the error correction capability requirements of the NAND Flash chip cost a lot of hardware resources.This Paper Proposed an area-optimized BCH decoder designed for NAND Flash.By reusing the key equation solver and the universal finite field multiplier in the Chien search module,the hardware overhead of the BCH decoder is reduced.The test on real hardware platform show that the data retention error in the NAND Flash presented nonlinear changes over time;and when the data retention time is few long,read disturb can slow down the whole error of NAND Flash.This paper proposed a Read Disturb-Aware Retention Error Correction Strategy.By increasing the Flash Correct and Refresh interval of physical blocks with more read disturbs,the number of system I/O operations is reduced and the I/O performance is improved.The implementation of BCH decoder on real hardware platform show that this design can reduce the hardware overhead by 13% with the same decoding latency.The Read Disturb-Aware Retention Error Correction Strategy implemented on the simulation platform shows that,compared with the latest RM(Refresh Minimize)strategy,the strategy can reduce the average read response time of SSD by 22%,write response time by 16% and request average response time by 20%;decrease erase operations by 40%,write operations by 23%,and page migration times by 51%.the number of system I/O operations is reduced and the I/O performance is improved efficiently.