Research On NAND Flash Controller Based On A New FEC Of LDPC

With the advent of the era of big data,the demand for data storage has soared.As a mainstream storage medium,NAND Flash has the advantages of high performance,high density,non-volatile,and low power consumption.However,the special internal structure of NAND Flash results in the need to design a dedicated controller for data management to suit a various types of storage systems.This paper focuses on the NAND Flash controller,including protocol and ECC techniques.The protocol mainly standardizes an efficient data storage management mechanism to meet the needs of high performance,low cost,stability,and ease of use.With its unique advantages,the eMMC standard is widely used in mobile devices such as mobile phones.LDPC(Low-Density Parity-Check Code)is a forward error correction coding(FEC)with excellent error correction performance and has been proposed for use in the ECC technology of NAND Flash,which ensures the reliability data storage.Therefore,this paper emphasized on the eMMC5.0 standard and study the NAND Flash controller based on a new FEC of LDPC,which mainly includes the following contents:(1)For the ECC module of the NAND Flash controller,an ECC architecture based on the cascade of error detection codes and LDPC codes was presented,to solve the problem of difficulties in obtaining soft information from NAND Flash.In the proposed error correction code scheme,the row and column error detection code is mainly used to generate relatively coarse soft information from the hard decision information read from the NAND Flash,and then perform LDPC soft decision decoding to improve the error correction capability.This paper designs an error correction code architecture with the code rate of 0.924 based on the cascade of error detection codes and LDPC codes.The simulation results show that the proposed row-column error detection code encoding can only provide rough soft information.However,compared with the hard information decoding scheme that does not use error detection code,the proposed scheme can improve the error correction performance.(2)A NAND Flash controller hardware design scheme based on a new FEC of LDPC was presented.According to the eMMC standard,a top-down design scheme is adopted to design the overall architecture of the eMMC,complete the functional simulation of 32 commands,and realize the main functions of the protocol.The designed eMMC controller mainly includes two modules: command processing and data processing.Command processing mainly completes command receiving,identification,execution,and response.The data processing module includes host DATA interface,data buffer,ECC,NAND Flash interface and other modules,with the emphasis on implementing ECC modules.Based on the proposed ECC architecture,An ECC module that is compatible with both hard-input and soft-input decoding is designed,which was applied to the eMMC controller.(3)A FPGA prototype of eMMC controller is designed and a hardware verification platform for eMMC controller is also implemented.The basic commands and data transmission had been tested separately to complete the verification of the basic functions of the eMMC controller.