Circuits and systems for solid-state data storage using highly scaled NAND flash memory

Solid-state data storage built upon NAND flash memory is fundamentally changing the memory and storage hierarchy for virtually the entire information technology infrastructure. This grand industrial trend is essentially driven by the steady bit-cost reduction of flash memory, which is enabled by continuous semiconductor technology scaling. Unfortunately, technology scaling makes flash memory devices subject to increasingly severe noise and distortion, which can largely degrade NAND flash memory storage reliability and performance. Error correction code (ECC) plays a critical role in ensuring overall system data storage integrity in presence of flash memory device reliability degradation. Conventional ECCs, such as the widely used Bose-Chaudhuri-Hocquenghem (BCH) code, have become increasingly inadequate as technology continues to scale down. Therefore, it is highly desirable to deploy a much more powerful ECC, such as low-density parity-check (LDPC) code. This thesis investigates the key design issues in practical application of LDPC code in flash-based solid-state drive (SSD).;Although LDPC code has had its success in commercial hard disk drives (HDDs), to fully exploit its error correction capability in SSDs demands unconventional fine-grained flash memory sensing, leading to an increased memory read latency. To address this important but largely unexplored issue. this thesis first investigates the impact of direct employment of soft-decision decoding LDPC codes in SSDs. Then this thesis presents three techniques to mitigate the LDPC-induced response time delay so that SSDs can fully benefit from its strong error correction capability. This thesis quantitatively evaluates these techniques by carrying out trace-based SSD simulations with runtime characterization of NAND flash memory reliability and LDPC code decoding. The study based on intensive experiments shows that these techniques used in an integrated way in SSDs can reduce the worst-case system read response time delay from over 100% down to below 20%. With the proposed techniques, a strong ECC alternative can be used in NAND flash memory to retain its reliability to respond the continuous cost reduction, and its relatively small increase of response time delay is acceptable to mainstream application users, considering a huge gain in SSD capacity, its reliability, and the price reduction.;Even in highly scaled NAND flash memory with seriously degraded reliability, the gradual wear-out and process variation of NAND flash memory makes the worst-case oriented ECC largely under-utilized most of the time. This thesis proposes to opportunistically leverage such under-utilized error correction strength to allow error-prone flash memory I/O link over-clocking, which can improve SSD speed performance. Its rationale and key design issues are thoroughly presented and studied in this thesis, and its potential effectiveness has been verified through hardware experiments and system simulations. Using sub-22nm NAND flash memory chips with I/O specs of 166MBps, extensive experiments were carried out and the results show that the proposed design strategy can enable SSDs safely operate with error-prone I/O link running at 275MBps. Trace-driven SSD simulations over a variety of workload traces show the system read response time can be reduced by over 20%. Further experiments with sub-22nm NAND flash memory chips reveal unique bit error characteristics of overclocked I/O link, based upon which this thesis develops solutions that can leverage the error characteristics to improve LDPC decoding performance. Results show that the developed techniques can reduce LDPC code decoding power consumption by 60% and reduce the decoding failure rate by over 2 orders of magnitude.