Research On Dynamic Scheduling For Decoding Of LDPC-Coded Multi-Level NAND Flash Memory Channel

NAND flash memory is preferable to the hard disk drive for the storage device and applied to the data center,due to its high access speed,low power consumption,nonvolatile property and high shock resistance.To improve the storage density and reduce the cost performance of NAND flash memory,on the one hand,the state-of-the-art process technique is applied.On the other hand,the multi-level cell(MLC)technique,which store multi bits in each flash memory cell,is exploited.However,this technique not only improve the storage density of NAND flash memory,but also increase the interference in NAND flash memory and lead the threshold voltage of flash memory to fluctuate.In NAND flash memory,one of the main reason of dynamic threshold-voltage variation of NAND flash memory is the influence of retention noise.To against the interference of flash memory,error-correcting codes(ECCs)technique is used.In ECCs technique,the Bose-Chaudhuri-Hocquenghem(BCH)code with hard-decision decoding algorithm is widely used in flash memory due to its fast decoding speed.Unfortunately,as the increase of interference of flash memory,the BCH code can no longer satisfy error-correcting requirement for flash memory.Hence,the more powerful ECCs with soft-decision decoding algorithm,such as Reed-Solomon(RS)code,low-density parity check(LDPC)code,have more and more attention from people.And due to approach Shannon limit,the LDPC code is widely employed in flash memory.Based on the dynamic decoding of LDPC-coded MLC NAND flash memory,the main research object of this paper is that an improved serial scheduling for decoding of LDPC-coded NAND flash memory is proposed.According to the characteristics of threshold-voltage distribution,this paper dynamically select updated sequence to achieve better decoding performance.The research and contribution are organized as follows:(1)The structure and the main interference of NAND flash memory is studied.Andwhen the interference works,the main characteristics of threshold-voltagevariation of flash memory are analyzed.(2)The serial and dynamic scheduling of LDPC code is researched.And theperformance of the serial and dynamic scheduling in the additive white Gaussiannoise(AWGN)channel is proposed.(3)In connection with the characteristics of retention noise,a new serial schedulingof LDPC code is proposed.This scheduling dynamically select updated sequenceaccording to the characteristics of threshold-voltage distribution.And theerror-rate performance and convergence speed of flash memory have animprovement.(4)In connection with the characteristics of retention noise,a new detectionalgorithm is proposed to improve the storage reliability of flash memory.