Designs Of LDPC Decoder Architectures For NAND Flash Memory

Quasi-cyclic(QC)low-density parity-check(LDPC)codes have become popular in NAND flash memories,owing to their excellent error correction performance and hardwarefriendly structures.Although Latin square is a well-known algorithm to construct LDPC codes for satisfying long code length and high code rate,it has a drawback of large submatrix that the hardware will be suffered from large barrel shifter and worse routing congestion in NAND(lash applications.On the one hand,array dispersion is an efficient way to construct Latin-based LDPC codes with a small submatrix size.On the other hand,this work proposed that array dispersion is more appropriate for the array-based LDPC codes.Array LDPC code is a kind of highly-structured QC-LDPC code,which provides a good balance of performance,complexity and throughput.In this work,a construction method of array-based LDPC codes using array dispersion algorithm is proposed.Array-based LDPC codes do not only benefit from the array property,but also a hybrid and efficient storage architecture due to their stair-like structure.For NAND flash applications,the code construction and decoder architecture of a(18300,16470)array-based LDPC code is illustrated in this paper,where a 2-level decision of LDPC decoding strategy is employed.The performance of both codes was first simulated on a software platform based on CUDA,and then on a hardware platform baesd on FPGA.The numerical results based have shown that the error floor of the array-based LDPC codes,which is under 10-11,is lower than the Latin-based LDPC codes in term of bit error rate(BER).Thanks to the well-structured array-based LDPC codes,we can conveniently apply column-based shuffle decoding(CBSD)algorithm for ease of implementation.The corresponding ASIC implementation results using TSMC 90nm library have proved that the decoder architecture of the array-based LDPC codes can achieve higher normalized-throughputgate-count-ratio(NTGR)compared to state-of-art works.