Control Logic Design Of NAND FLASH Array Operation

Due to the characteristics of large storage capacity and low power consumption,NAND flash chip has gradually become the mainstream choice in the field of large-scale memory.In order to further improve the storage density,people reduce the device size and adopt 3D structure,which leads to more serious inter cell interference,increases a series of operational control algorithms and complexity of NAND flash array,thus improving the design requirements of control logic.The traditional implementation of array operation control logic based on state machine has a long design cycle and low flexibility of modification,which is not conducive to the continuous optimization of operation control.However,the control logic implemented by MCU has a long control time,which affects the overall performance of reading and writing.This paper is based on NAND According to the control principle of flash array,the internal controller of dual MCU structure is selected and designed to speed up the reading and writing operation.Through the design of peripheral signal control mode,the logic design of array word line control is realized.The voltage control is specific to each word line,and the page buffer adapted to the method of C/F reading is designed in the direction of the word line,so as to realize the unified control of the bit line and selection control operation.In the aspect of array operation,based on the designed control logic,the dynamic bit line voltage write operation and C/F read operation are used to realize the read and write operation of the flash array,and finally the simulation is carried out.The design is based on ONFI industry standard,using MLC array model for functional simulation verification.The simulation results of unit reading and writing show that there is no error in data input and output during the process of writing and reading,and the function is implemented correctly.The simulation time of reading and writing is 60us and 980us respectively.The standard process of 0.18?m is used in the evaluation of resource use in the DC integrated tool.The results show that the total area of the controller is 378292.6?m~2,the average power consumption is 16.7385mw,compared with the single MCU controller,the increased part is less than 10%compared with the general 512gb flash chip,which meets the expected effect in the acceptable range.