Research And Optimization Of BCH Codec In NAND Flash Control System

With the development of technology and the popularity of digitalproducts, the U-disk with encrypt function has become necessary to bothindividuals and institutions. NAND Flash is used in U-disk as the mainstorage media, but this storage media may have random errors, so the datamust be encrypted before stored into it. Because of the good ability tocorrect random errors, BCH code is widely used in the NAND Flash errorcorrecting, this code also has strict math structure and easy to generate. Soit is necessary to design a security chip with powerful BCH encoder anddecoder.This paper begins with the research of BCH codec’s algorithm andthen has a deep study in the structure of NAND Flash. According to thedemand of the security chip, a series of special targets are decided. Afterthe study of algorithm, we develop a software program in C language, thisprogram is used to make sure our understanding of BCH’s algorithm iscorrect, and also it is a good preparation to the IP’s hardware design. We use the high bits configurable parallel design plan to develop the BCH IP.During the design, the whole project is divided into several modules andeach module has a unique function. To the decoder module we use theinversionless Berlekamp-Massey algorithm and parallel iterationalgorithm to optimize the circuit. Meanwhile, to the finite field multiplierwe use the modified greedy algorithm to optimize the area and use thebalanced tree structure to optimize the delay.This paper’s design is based on the standard IP design’s flow, thisBCH IP is going to be used in the security chip. Its largest correctingability can correct24bits errors in each1024Bytes data. This IP also has alarge variable range of configurable parameters, the data range can be512Bytes and1024Bytes, the error correcting range can be8bits,16bits,24bits. We use a dividing method to make the encoder/decoder can workwhen the page’s data capacity is512,1k,2k,4k,8k Bytes. In this paper,the innovative work reflects in the following four aspects:1) Use the parallel and configurable design plan to develop a softwareprogram in C language and finish the RTL writing.2) The largest correcting ability can reach24bits/1024Bytes.3) Optimize the design from three aspects: algorithm, area, delay,propose a new method to modify the greedy algorithm to optimize the area.4) According to the standard IP design’s flow, accomplish a BCH IPwhich is used in the security chip.After finishing this IP’s design, lots of verification methods are usedto make sure its correctness. This BCH IP can reach a commercial level,and will have a positive impact to the people’s security needs.