Research On Hybrid NAND Flash Storage System Based On Asymmetric Channel Technology

The development NAND Flash technology exacerbates the contradiction betweenthe capacity and performance of NAND Flash. The capacity of NAND Flash is keepincreasing as well as its unit’(block and page), but the unit of file system’ operation isstill one sector. Then one physical page contains much more logical sectors, thosesectors may update separately, but the page can only be programed once, and the eraseunit is one block which contains several pages. Thus the re-write problem is muchworse than ever, and need more efficient management way to organize the multi-NANDFlash chips.in addition, with the increasing of NAND Flash capacity, the process ofNAND Flash is decreasing, its chief consequence is that the times of program/eraseoperation is reduced. This also calls for high NAND Flash managing efficiency.Moreover, the growth of data size is very quickly, nowaday’s architecture of NANDFlash can not fulfill the need of data storage.Based on the problems analyzed above, this paper designs an asymmetricarchitecture for storage system based on multi-channel NAND Flash. The asymmetricarchitecture reflected in asymmetric channel and asymmetric NAND Flash. Asymmetricchannel achieved by combining some of the NAND Flash channels together to form asuper channel. The unit of the super channel is larger than ordinary one, so there will beless entry in the mapping table in the condition of same capacity, thus RAM capacitycan be reduced. Asymmetric NAND Flash intends to take full advantage of SLC andMLC NAND Flash which have better performance and larger capacity respectively.Based on the proposed asymmetric architecture, address translation and commandscheduling methods also be designed.Simulation system is designed based on DiskSim and SSD Model developed byCMU and Microsoft respectively. Under the proposed condition of this work, themapping table size is reduced by25%in4channels system and50%in8channelssystem. The size of RAM is about one in tenth of the ordinary architecture. In therandom performance aspect, the proposed architecture uses only25%SLC achievingalmost the performance of pure SLC system. Sequence performance is between thembut higher than the ordinary one.