Design And Implementation Of MCU Applied To 3D NAND FLASH Control Logic

With the development of video and big data applications,the demand for low-cost and large capacity NAND flash memory is increasing.NAND flash memory is composed of two parts,a memory array and control logic,where the control logic is closely related to the storage mechanism and process parameters of the memory array.With the increasing difficulty of improving process of planar NAND flash,the industry has changed its research direction to 3D NAND flash,which has a lot of memory stacking layers and higher integration,so the design of its control logic circuit is also more complex.Because of the different process parameters of different flash array,the control logic cannot be universal.Therefore,each time the 3D NAND flash array technology develops,the control logic must be redesigned,and its design complexity,design cycle,and cost can no longer meet the needs of the application.In this paper,aiming at 3D NAND flash,based on the flash process line of YMTC,a well-known memory company,we try to research and design the control logic based on MCU architectureIn order to meet the compatibility of control logic with different array under the process line and the flexibility of transplanting control logic in the future process upgrading,this paper completed the design and optimization of control logic based on MCU scheme.First,this paper designs the control logic architecture of dual-core MCUs,and the dual-core parallel execution improves its control efficiency;Next,this article delves into the storage mechanism of the different memory array under the process line,and designs the MCU RISC instruction set,which specifically includes the operation code designed as instructions based on common fine-grained storage operations,and the implementation related to specific storage process parasitic parameters Into instruction operands.At the same time,the data transfer instructions and conditional branch instructions are optimized in combination with the specific operations of flash.Immediately after,we carried out the MCU core design,including arithmetic logic units,registers,and controllers,and used three-stage pipeline processing on the data path to improve the execution efficiency of memory chip operations.Finally,based on the designed control logic circuit,this paper implements the read,write,and erase operations of 3D NAND FLASH,which is used to verify the function and performance of the logic circuit.After the function verification,the logic circuit is implemented by ASIC.It is synthesized under YMTC 0.18?m CMOS standard process,the chip area is 243972,and the power consumption is 2.3099 m W at a working frequency of 50 MHz.Compared with the industry memory,the operation time of the control logic designed in this paper has reached or even exceeded the industry advanced level.