Research And Implementation Of Large-capacity NAND Flash Array Management Technology

Data storage plays a pivotal role in the era of big data.Only when data is stored safely and reliably can data be analyzed and used.However,with the development of science and technology,the amount of data generated by various applications is increasing,and the speed is getting faster and faster.This puts forward new requirements for data storage devices: large capacity and high storage bandwidth.The storage array made up of NAND Flash has not only large capacity,high speed,but also excellent anti-vibration performance,and it can just meet these new requirements.However,due to the defect of NAND Flash itself: with bad blocks,the data bits will flip.Therefore,these defects must be controlled and managed when using NAND Flash as a storage medium.In the traditional management technology,the bad block management retrieval speed is slow,and it needs to consume a large amount of FPGA RAM resources.The error correction algorithms are mostly serial codecs,and the speed is too slow for high-speed applications.These are suitable for single-chip NAND Flash.The technology is no longer applicable to the management of NAND Flash arrays,so this topic is to study and implement the application of these management technologies in NAND Flash arrays.This topic researches the management technology of NAND Flash array at the hardware level,designs a NAND Flash array memory card according to actual needs,and designs a programming pipeline technology according to the structural features of NAND Flash to improve the programming speed of NAND Flash.The bad block for NAND Flash arrays adopts the management strategy of bad block skipping.Based on the research of other bad block table storage schemes,propos ing unique scheme: storing the bad block addresses,the address is divided into two parts,one part is the data bit of RAM,and the other part is the address bit of RAM.This method not only speeds up the retrieval of bad blocks,but also greatly saves the RAM resources of the FPGA.For bit flipping of NAND Flash,BCH error correction algorithm is used for error detection and correction in this topic.A shortend BCH code(1112,1024,8)is designed,and the encoding and decoding speed is accelerated through 32-bit parallelization.First,we verified the BCH algorithm with software,the correctness and completeness of the BCH algorithm are verified.Then the BCH firmware is designed,simulated,and finally applied to the actual scenario.The large-capacity NAND Flash array management technology researched in this project has been applied in the phased array radar test experiments with actual radar.The experimental results show that the capacity and bandwidth of the memory card designed by this subject can fully satisfy the radar test requirements,and the research NAND Flash array management technology can guarantee t he stability and reliability of the data.