Study On Architecture Of ECC Codes For NAND Flash Memory

With the development of microelectronic technology, the storage density of NAND flash increases significantly,which leads to a sharp rise of error rate。The traditional error correction code has been unable to meet the requirement of NAND flash memory. Low-density parity-check(LDPC) codes is starting to be used for NAND flash because of their excellent performance and Low decoding complexity,and widely considered to be the next generation of error correcting coding scheme of NAND flash memory.But NAND flash has the characteristics of high bit error rate, redundancy of small space,fast data transmission speed,which make it difficut to apply LDPC codes in NAND flash memory. Therefore,it has great practical significance to study the construction method of LDPC codes with high-rate and high-performance and their coding algorithm which has low coding delay.The present construction methods of LDPC codes for NAND flash memory only had eliminated cycle 4 without considering the number and distributionof cycle 6.There were lots of cycle 6 in these high rate LDPC codes,Which leads the low performance of these LDPC codes,large search volume and very low success rate etc. This paper first developed a construction method of QC-LDPC codes with high rate and optimization of short cycle. In this method,we can effectively reduce cycle 6 when eliminating cycle 4 through considering the number and distribution of cycle 4 and cycle 6 synthetically.And the search volume was also greatly reduced with with one hundred percent success rate. Then according to the parameters of NAND flash memory devices, QC-LDPC(69615,66897) code, QC-LDPC(34528,32864) code, QC-LDPC(1726416432) code and QC-LDPC(86328216) code were constructed according to developed construction method,and were applied in NAND flash memory.Simulation result showed that, compared to the existing(69615,66897)EG-LDPC codes for NAND flash and QC-LDPC code(34520,32794) presented by Reference [31], the lifetime of NAND flash memory can be increased 18% when the constructed LDPC codes was used。In respect of coding algorithm, serial coding algorithm of QC-LDPC has very high delay time,which unable to meet the high data transmission speed of NAND flash memory. Therefore an improved 8 bit parallel coding algorithm was proposed, which solves the problem of high coding delay time and incompatible interface when using the serial coding algorithm. Simulation results showed that, the coding delay time of the proposed coding algorithm in this paper drop to 1/8 of the original’s with less hardware overhead.And the designed encoder has a data transmission speed of 319MB/s.