Optimizing Performance For 3D MLC Flash Memory With SLC Blocks

3D NAND flash is more appreciated for its massive capacity and significant performance and SSDs(Solid State Drives)based on 3D NAND flash are deployed as dominant storage devices in data centers.However,3D flash brings in the “Big Block” Problem.On the one hand,3D flash blocks consist more pages than 2D flash does,which in turn increases the erase operation latency and the number of pages copied during GC(Garbage Collection).Thus the GC penalty is much heavier for 3D flash.On the other hand,the 3D flash page size increases,which prolongs the delay of data transfer when 3D flash serves small requests.Existing works focus on reducing the number of migrated pages with sub-block GC strategies,which deeply depends on the distribution of valid pages inside the victim block.And many proposals buffer and merge small requests to reduce the the delay of data transfer,which suffers from a heavy overhead for data management.Based on the above analysis,we develop a NAND flash controller and propose a flash translation layer called SCS-FTL.The flash controller supports the parallelism and advanced auxiliary operations of flash.With the supports of flash controller,SCS-FTL exploits the characteristics of SLC-mode to accelerate the GC procedures,which doesn't rely on the distribution of valid pages inside the victim block.Moreover,SCS-FTL divides a flash page into subpages to serve small requests,which avoids the overhead for data merging.We implement SCS-FTL in the case of both block-level FTL and page-level FTL.Experimental results show that compared with state-of-art designs,SCS-FTL reduces the average read response time by 19.8% and 37.3% on average in the case of block-level FTL and page-level FTL,respectively.