Design And Research Of A Fast Transient Respone Low Dropout Regulator For 3D NAND

As a kind of nonvolatile memory,3D NAND has been widely used in USB flash disk,PCs,mobile phones,data center and storage system of intelligent driving car.With the increasing demand of storage,3D NAND will continue to maintain its leading market share by virtue of its high storage density,low power consumption,fast read-write speed and other characteristics^[1].Low Dropout Regulator(LDO)is a voltage supply module in 3D NAND.When the working state of the system changes,it must respond quickly to load changes to prevent the load module from entering the wrong operating state.Therefore,the research of LDO with fast load transient response has significant scientific research and market value.This paper introduces the basic working principle and main parameters of LDO,firstly,and then designs a LDO with fast load transient response capability according to the requirements of 3D NAND.This paper uses three methods to improve transient response speed.Firstly,the class AB error amplifier is used and the difference of charge and discharge current is amplified proportionally at the output of the operational amplifier by current mirror,so as to improve the adjustment speed of the grid of power tube.Secondly,the transient enhancement circuit is added.Its working principle is that when the LDO's load changes,it selectively opens a charging or discharging path independent of the error amplifier-power transistor main loop to assist the error amplifier to adjust the power transistor,so as to improve the transient response speed.When the adjustment is finished,the transient enhancement circuit is closed to reduce the power consumption of the system without affecting the normal operation of the main loop.Thirdly,dynamic tail current source is used.Compared with the fixed bias tail current source,the dynamic tail current source can increase the power supply capacity of the tail current source of the error amplifier when the load changes,so as to improve the adjustment speed of the power transistor.When the output voltage is stabilized,the tail current source will also be out of the temporary amplification state,so as to reduce the power consumption of the system in stable operation.In addition,because this paper contains two voltage bias nodes and one reference voltage node,I also design a bandgap voltage reference circuit to provide the three voltages.The circuit is implemented with 0.188)process,and simulated by Cadence Spectre.It can be seen from the simulation results that under different process corners and temperatures,the fast load transient response LDO designed in this paper improves the overshoot voltage by 44.5%?47.6%,the overshoot recovery time by 37.6%?39.2%,the undershoot voltage by 60.7%and the undershoot recovery time by 49.8%compared with the traditional off chip capacitorless LDO used in 3D NAND.