Design And Implementation Of High Speed PCIE Data Acquisition Card Based On Zynq

As an important part of information processing,high-speed data acquisition has been applied in many aspects.Especially in the field of military electronic countermeasure,the electromagnetic signal detected by electronic reconnaissance has shown the trend of "big data".With the emergence of various complex wideband radar technologies,and the in-depth application of artificial intelligence in electronic reconnaissance signal processing,higher requirements are put forward for data acquisition.Under the background of radar emitter identification project,this paper studies and designs a PCIe high-speed data acquisition card based on zynq,which can realize high-speed acquisition,transmission and storage of signals in the frequency band,and ensure that the transmission rate meets the design requirements and the overall performance is reliable and stable.According to the actual processing requirements,the high-speed data acquisition card designed in this paper adopts the structure of carrier card and sub card.According to whether the input signal is analog signal or digital signal,the ad sub card and optical fiber sub card are flexibly replaced for matching.The carrier card and the sub card are connected by highspeed interface.The data of the sub card is received by the acquisition card.After the internal data preprocessing of the zynq processor,the data is transmitted to the emitter signal recognition platform through the PCIe bus interface to complete the subsequent processing.The main contents of this paper include:(1)Completed the hardware design of the acquisition cardThe hardware design of acquisition card includes the circuit design of carrier card and sub card as well as the chip selection and configuration.Zynq7000 soc is selected as the main control chip for the carrier card.The zynq7000 chip uses FPGA + ARM architecture to realize data reception and data processing on a single chip.FMC connection mode is selected to support the data access of different sub cards.DDR3 is designed as a large capacity FIFO in the process of high-speed data transmission to achieve data rate matching.The communication between the acquisition card and the emitter signal identification platform is realized through the PCIe bus interface.According to the needs of the radar emitter identification project,the ADC chip is selected to complete the design of the ad sub card,and the signal is led to the zynq chip through the FMC interface;the optical sub card realizes the transfer between the optical interface and the FMC interface.(2)Completed the software design of the acquisition cardSoftware design includes logic design,embedded software design and upper computer design.The logic design mainly completes the collection and transmission of high-speed data,studies the design and implementation of the transmission and storage of ad data and optical fiber interface data,completes the logic design of each module,and enables each module to realize data exchange and high-speed data transmission.In order to reduce the burden of subsequent data processing,the embedded software design can realize the preliminary data processing through the work of kernel migration,system migration and image burning in Ubuntu environment.The design of the upper computer mainly realizes the detection and initialization of the acquisition card and the storage of the received data.(3)Completed the high-speed data transmission performance test of the acquisition card.Through the actual test,the data transmission rate and error rate of the acquisition card can meet the requirements of the radar radiation source,providing the basis and reference for the subsequent design and implementation of the data acquisition card.