Design Of PCIE DMA Bus Transferring In Data Acquisition System

With the development of information technology, data acquisition has been used in telecommunication, network, industrial control, automation, medical treatment, biological science and many other areas as a key technology. In feet, data acquisition usually works as a critical module in different situations, like data acquisition modules in wireless base station, high-definition image processing in military aerospace, high performance digital storage oscilloscope, radar target detection, and DNA spectrum analysis. However, with the increase of data amount, data acquisition system has to meet the bigger challenge, especially focusing on the acquisition, storage, transmission and process of data.Background of this paper is the project of designing a data acquisition system with the basis on the protocol of Wireless Body Access Network. All of the data processing in baseband is operated on the general CPU and the data processed by the CPU is transmitted to FPGA through PCIE bus interlace. Finally, the Digital-Up-Converter, Digital-Down-Converter, Analog-to-Digital and Digital-to-Analog blocks are implemented on the FPGA. What is focused on in this paper is the design of DMA Coniroller based on PCIE interface. This means mass data stored in DDR3 SDRAM in data acquisition system is transmitted to PC by the means of direct memory access, and’ real-time data analysis and management is operated on PC software. In fact, the performance of PCI-Express DMA has a great influence on the real time working of the system.The interface of DMA Controller with PCI-Express second-generation standard and four-lane data path is realized in our project. The PCIE IP provided by Xilinx is utilized to generate a PCIE endpoint device. Module of data packing and unpacking and the related interface are designed in transaction layer. Different from the traditional design which usually adopts FIFO and RAM as the local storage, DDR3 SDRAM with 8GB capacity is utilized in this paper. This can actually enhance the data storage in our system. According to the PCIE protocol, Memory-Read request packet should be first transmitted when endpoint device is used as the bus mastered device in PCIE bus domain. Polling mechanism of request packet is put forward in this paper innovatively, which can avoid the occurance of overflow in memory space. Finally, the interface conversion between DMA controller and DDR3 Controller is realized and asynchronous FIFOs are added across the two different clock domains. This can avoid the occurance of metastable state effectively.The PCIE driver based on Linux PC is realized in this paper. Different from the traditional design, a new method which is fit for enormous amount of data under DMA transmission is presented. At first, the data to be DMA transferred is divided into many blocks with the size of 4MB. Then, the variables which is relevant with DMA operation is organized into the DMA operator which is expressed with the Linked List structure. Finally, the completion mechanism in Linux kernel is used to realize the operation of DMA transmission in DMA space and data copy in user space in parallel. The method of PCIE driver proposed in this paper can reduce the time cost.We choose the product of BEEcube company, miniBEE(including FPGA processing board, Linux host PC, and the PCIE bus between PC and FPGA), as our development platform because of its high performance of FPGA-based prototyping. We verify the function of logic design by the ChipScope software which can detect the inner signal of the FPGA, and also test the correction of PCIE driver by writing the application program. According to our test, PCIE DMA controller can reach 965 MB per second when transmitting data from PC to FPGA and 882MB per second when transmitting data from FPGA to PC which approach the theoretical speed of PCIE bus much closely.