The Processor, Based 2FFT's High-speed Configurable FPGA Implementation Study

Digital signal process(DSP) replaces tranditional analog signals process systems in many area. As the basic module FFT is bottle-neck of the signal process. Researching more high speed and performance FFT processor is a hot research spot in the world. At the moment high speed FFT can be realized on DSP, FPGA and ASIC IP. The FFT modules' speed can reach several ten to hundred millionth seconds. For example, the FFT processor using TI DSP reaches 56 millionth seconds, but several DSP's are needed. Xinlinx releases its new FFT module based on 800 million-gate VertexII, whose speed achieves 1 millionth second.The Research and FPGA Realization of High-Performance Configurable FFT Processor is presented in this dissertation. It includes the system architecture design and subsystem architecture design, algorithm verification and implementation. At last a test platform was builded by FPGA and PC, and the verification of the FFT processor has been carried out. Computing 256-point FFT using this FFT processor can reaches 9.56 millionth seconds. So this high speed FFT processor in the dissertation can be applicated in high and real time process fields such as digital signal process, telecom system, etc.These works are presented in this dissertation:1. This paper has collected lots of papers related to FFT modules, and analysised these FFT processors.2. A novel structure named symmetrical PingPang structure based on PingPang structures has been presented. So the efficiency of the buttfly core could be highly enhanced.3. Our FFT processor can be configured. The max computing point is 256, and the point that can be set is the power of 2. This character increases the flexibility of the FFT processor.4. An antioverflow mechanism based fixed-point core has been designed. The word length is 16 bits, and the word length of the RAM is 17 bits. Contrastedwith the 1/2 cut-tail, precision has been increased. And this paper has carried out system simulation that has proved that the precision can be enhanced under not adding time-delay.5. A high-speed 16bits*16bits multiplier has been developed, which introduces Modified Booth Arithmetic (MBA), Wallace Tree and 4:2 Compressor, Pseudo 4:2 Compressor and Square Root Carry-Select Adder.6. The whole structure has been developed. The algorithm is realized by VerilogHDL and simulated by VCS, and the testbench has also been designed.7. Having been realized on FPGA of VertexII proves the FFT's max frequencyreach 112.007MHz. The total time to finish a 256-point FFT is 9.57us .