Research And Implementation Of High Speed And Configurable FFT/IFFT Converter

With the fast development of mobile communication technology, the data transmission of the telecom industry is experiencing explosive growth. In the aspect of technology upgrading, resource consumption and cost maintenance, the traditional wireless access network architecture has serious disadvantage. These problems can be solved effectively by C-RAN architecture which is a new kind of wireless access network architecture.FFT/IFFT converter is used in baseband processing module of C-RAN architecture, which acts as a part of signal modulation and demodulation. The current research of C-RAN architecture based on TD-LTE protocol, so FFT/IFFT converter needs to support different kinds of points. Besides, it has certain requirements of higher data throughput, lower hardware cost and higher precision of data processing.To start with, the structures and characteristics of C-RAN architecture are researched and two forms of C-RAN architecture are analyzed in this thesis. TD-LTE protocol and OFDM technology involved in C-RAN architecture are also briefly introducesd and requirements of FFT/IFFT converter design is analyzed.Secondly, different kinds of FFT algorithms, the hardware implementation structure and the representation of processing data are analyzed and compared. Considering the requirements of C-RAN architecture, mixed radix algorithm and structure of serial production line are proposed. It can meet high data throughput and minimize the consumption of hardware resources. Through modeling and simulation of the fixed point and block floating point data representation in Matlab, the data representation of block floating-point is adopted in the converter. On FPGA platform, a high speed and configurable FFT/IFFT converter is presented in this thesis and the butterfly operation module and rotating factor module are optimized to complete RLT level code input.In the end, complete the simulation function by building the simulation platform as well as integration, layout of the RTL design, wiring and static timing analysis are done by using the Quartus II software of Altera Company. At last, board level design validation is finished in Altera DE4 development platform.The present research of C-RAN architecture digital front-end adopts the 250 MHz clock of PCIe, whose data throughput reaches 8 Gbps. The initial time to complete an OFDM symbol is 66.67 us. It needs to support six kinds of points FFT/IFFT transformation, including points of 128、256、512、1024、1536 and 2048. It has higher data conversion accuracy and less resource consumption. In this thesis, the design of FFT/IFFT converter in Altera Stratix IV maximum working frequency reaches 321 MHz. The rate of maximum data throughput is 10.2 Gbps, the initial delay of convert of 2048 is 21 us. As for the data conversion accuracy, SQNR is above 54 db and the hardware resource consumption is lower. Through hardware testing, the FFT/IFFT converter put forward by this paper can meet the requirements of C-RAN architecture.