A FPGA-based Traffic Generator For Network Performance Measurement Of High-speed Ethernet Switch

Network traffic test is one of the most important parts for the evaluation of communication network,and the appropriate network test tool plays a great role in the evaluation of network system.With the development of network bandwidth,the content configuration scheme of test flow,the transmission rate and precision of test flow are difficult to meet the requirements of equipment testing under the million Gigabit network.On the one hand,the frontier test flow generation technology to meet the requirements of high generating rate and high sending accuracy is monopolized by the industrial giants.On the other hand,the test traffic generation technology is integrated into the black box products,which are not flexible and extensible for the ever-changing testing requirements,they are difficult to fit and can not be evaluated correctly and adequately for the performance of network equipment.In view of the above two kinds of challenges,we design and realize the traffic generating module for network test of high speed Ethernet switch.In this thesis,the current flow analysis techniques are investigated.In combination with the application background of high speed Ethernet switch and the configuration feature of flow model,a set of high speed configuration of test data is designed.And based on the scheme,the test flow generation technology is researched and designed.The main work and innovation of this thesis are:Based on the analysis of the flow analysis technology,the characteristic configuration process of the test data flow is divided into two parts:the stable configuration and the shifty configuration,and the configuration process is split according to the respective advantages of the software and hardware implementation.In addition,we propose the optimal configuration scheme of the multi-byte variational fields by analyzing the characteristics of the shifty configuration of the flow-level model.Furthermore,the problem of multi-channel frame merging in network transmission under the condition of Gigabit Ethernet is optimized.The simulation verifies that the design of this kind of scheme improves the performance of test flow dispatch.We design and implement a FPGA-based test flow generation module for high speed Ethernet switch.Based on the function simulation of each module of FPGA engineering,we focus on the realization of traffic generating module.Comparing the flow generation function of IXIA400T commercial network tester to the system test,the test results show that the design correctly realizes the test flow generation of Gigabit Ethernet,consumes less resources of the hardware platform,and the test flow loss rate is below 0.3%.When the packet size is greater than 128 bytes in mega cases,the performance of test flow dispatch is close to the theoretical value.Aiming at the test flow characteristics of high speed Ethernet,the thesis completes the design of the test flow generating module based on the high speed Ethernet switch,and realizes the Generation and dispatch of the test flow under the super Gigabit condition under the condition of guaranteeing the throughput and the small packet loss rate.