Design Of Rate-compatible Quasi-cyclic LDPC Codes Synchronizer And FPGA Implementation

LDPC codes are good codes that approximate the Shannon limit. LDPC codes have some advantages such as low decoding complexity and low error floor, which make LDPC codes have a good prospect in reliable transmission of information. Quasi-cyclic low density parity check codes are a subclass of LDPC codes that can be encoded by the shift registers, which greatly reduces the coding complexity, and decoding is simple. A communication system based QC-LDPC codes, QC-LDPC codes are in frames for transmission and decoding, there is transfer-delay in the transmit ssion, which will result in the frame offset in the received information, so the QC-LDPC codes frame synchronization for the communication system is extremely important.The author uses theoretical analysis and simulation of hardware to study the QC-LDPC code decoding algorithm and frame synchronization. The major work done in the following areas:Firstly, LDPC decoding algorithms are introduced systematically. The updated formula of BP-based algorithm of LDPC codes interfered by the pseudo-random sequence is analyzed.Secondly, according to the characteristics of parity-check matrix of LDPC codes, two pilotless frame synchronization methods for LDPC codes are introduced. Using pseudo-random sequence to interfere the QC-LDPC codes is in order to eliminate the error when synchronizing.Finally, based on the characteristics of the two pilotless frame synchronization methods, there are two designs for rate-compatible QC-LDPC codes synchronizer. One of them can reuse some of the resources of the decoder, and the design and implementation of the other one are simple. The FPGA design and gate-level simulation results of two synchronizer are given.