Research On Flash-based Solid-state Disk With DDR3 Interface

In the Big Data era,a large number of data-intensive applications require higher performance storage system.While the traditional disk storage,as the representative of the external storage device,has been unable to meet the growing demand in performance,information storage and processing is facing a huge challenge.Flash-based SSDs have many excellent features such as fast random access,high capacity,small size,high resistance to shock and vibration etc.It can be applied to large-scale data storage system and has the advantage of satisfying the performance requirements.With the flash memory technology develops,Flash-based SSDs has been more and more widely used in various storage areas.After several generations of SSDs technology development,flash-based solid-state disk has become increasingly mature.Researchers have also placed higher expectations on it.In the future,higher performance,higher capacity flash-based solid-state disk technology will become a development trend.The traditional SATA or PCIE SSDs,because of the external bus protocol in it's I/O path,so that the path is very long,which affects storage performance.In this paper,we use the DDR3 interface to design a new type of flash-based SSDs,which directly connected to CPU and bypass all of external storage protocol,shorten the I/O path,so that it can obtain a significant increasing in performance.The main work and research results of this paper are as follows:First,we in-depth analysis of the working principle of DDR3 memory and it's bus protocol.We study the memory bus timing,and have a profound understanding on the DDR3 interface.Second,we designed the overall structure of flash-based SSDs with DDR3 interface.The structure of SSDs include main controller,DRAM as data buffer and eMMC as the flash memory.We use Zynq to implement main controller and use eMMC to implement flash array.We designed the working mechanism of SSDs,and designed the DDR3 interface controller mechanism,the DRAM data buffer mechanism and the eMMC controller mechanism in detail.Third,we designed the DDR3 interface controller,which parse the memory bus signal and complete the interaction with the memory controller correctly.We verified the function-correctness of the DDR3 interface controller,and test it's performance in read and write,which showed a very high bandwidth utilization of DDR3 interface.