Design Of Interface Circuit Compatible With DDR3 And DDR4 Memory Standards

In recent years,with the development of the integrated circuit industry and the growth of the iterative speed of electronic equipment renewal,the development of memory technology is also a sharp advance.After the introduction of the Intel Celeron,AMD K6 processors and associated motherboard chipsets,EDO DRAM(Extended Data Out Dynamic Random Access Memory)performance does not match the processor,and the processor needs higher standard memory to meet its needs,so the memory technology enters the SDRAM(Synchronous Dynamic Random Access Memory)stage.With the increasing level of memory technology,the requirements for its memory interface become higher and higher,and it is necessary to design a DDR(double data rate)memory interface circuit which matches its function and has better performance.This paper designs an interface circuit compatible with DDR3 and DDR4 memory standard.First,it summarizes the development history of memory and memory interface,and expounds the present situation of research on interface circuit at home and abroad;Secondly,the basic theory of interface circuit is introduced,the research and comparison of the DDR3 interface standard SSTL(Stub Series Termination Logic)and DDR4 interface standard POD(Pseudo Open Drain)are carried out,and the significance and principle of ODT(On Die Termination)impedance matching and OCD(Off Chip Driver)impedance matching are introduced.This paper focuses on the design of ZQ calibration module,input I/O module and output I/O module,and the simulation verification of each module.The paper's innovation are as follows:1)aiming at the deficiency that ZQ calibration is only applicable to a single standard in common interface circuits,a ZQ calibration circuit compatible with two memory standards,DDR3 and DDR4,is designed.By using different number of driving units and external resistances for calibration through coding control,the difference between the on-chip terminal impedance/output impedance and the expected value is maintained at ±4%;2)Afterthe standard voltage deceleration of DDR4 and the transmission rate has beenincreased,the previous input receiver cannot satisfy the problem of receiving highspeed data transmission.By adopting a set of differential pairs and using thick gate transistors only at the input end and thin gate transistors at the other positions,a new DDR4 input receiver circuit is designed.The highest working frequency of the circuit can reach 1333 MHz and the output signal can maintain a good duty cycle.3)For the drawback of traditional level-shifting circuit,which can only be switched at certain voltage,and the transmission signal is slow,a new level shifter is designed,which can be compatible with DDR3 and DDR4 memory voltage standard,by reference to traditional level-shifting circuit,Add fast response module and duty cycle regulator module so that the circuit can operate at a maximum frequency of 1066 MHz in DDR3 mode,1333MHz in DDR4 mode,and the output signal duty cycle can be maintained at 50%±1% in both modes for different input I/ O supply voltages.The interface circuit is designed using the UMC 28 nm process with voltage range of 1.0V~1.5V and operating temperature of-40?~125?.Through the simulation verification of Spectre software,the result shows that the interface circuit can complete the communication between DDR3 and DDR4 memory and CPU,as input I/O,the circuit can receive off-chip signal at the highest frequency of 1066 MHz in DDR3 mode;In DDR4 mode,the maximum frequency at which an off-chip signal can be received is 1333 MHz.As output I/O,the circuit can transmit signals out of the chip at a maximum frequency of 1066 MHz in DDR3 mode;In DDR4 mode,the maximum frequency at which signals can be transmitted out of the chip is 1333 MHz.